Lines Matching +full:0 +full:x6040
49 { 249600000, 1800000000, 0 },
53 { 595200000, 3600000000, 0 },
57 .l = 0x3e,
58 .alpha = 0x8000,
59 .config_ctl_val = 0x20485699,
60 .config_ctl_hi_val = 0x00002261,
61 .config_ctl_hi1_val = 0x2a9a699c,
62 .test_ctl_val = 0x00000000,
63 .test_ctl_hi_val = 0x00000000,
64 .test_ctl_hi1_val = 0x01800000,
65 .user_ctl_val = 0x00003100,
66 .user_ctl_hi_val = 0x00000805,
67 .user_ctl_hi1_val = 0x00000000,
71 .offset = 0x0,
88 { 0x1, 2 },
92 .offset = 0x0,
110 { 0x3, 3 },
114 .offset = 0x0,
132 .l = 0x21,
133 .alpha = 0x5555,
134 .config_ctl_val = 0x20485699,
135 .config_ctl_hi_val = 0x00002261,
136 .config_ctl_hi1_val = 0x2a9a699c,
137 .test_ctl_val = 0x00000000,
138 .test_ctl_hi_val = 0x00000000,
139 .test_ctl_hi1_val = 0x01800000,
140 .user_ctl_val = 0x00000100,
141 .user_ctl_hi_val = 0x00000805,
142 .user_ctl_hi1_val = 0x00000000,
146 .offset = 0x1000,
163 { 0x1, 2 },
167 .offset = 0x1000,
185 .l = 0x32,
186 .alpha = 0x0,
187 .config_ctl_val = 0x08200800,
188 .config_ctl_hi_val = 0x05028011,
189 .config_ctl_hi1_val = 0x08000000,
193 .offset = 0x2000,
210 .l = 0x29,
211 .alpha = 0xaaaa,
212 .config_ctl_val = 0x20485699,
213 .config_ctl_hi_val = 0x00002261,
214 .config_ctl_hi1_val = 0x2a9a699c,
215 .test_ctl_val = 0x00000000,
216 .test_ctl_hi_val = 0x00000000,
217 .test_ctl_hi1_val = 0x01800000,
218 .user_ctl_val = 0x00000100,
219 .user_ctl_hi_val = 0x00000805,
220 .user_ctl_hi1_val = 0x00000000,
224 .offset = 0x3000,
241 { 0x1, 2 },
245 .offset = 0x3000,
263 .l = 0x29,
264 .alpha = 0xaaaa,
265 .config_ctl_val = 0x20485699,
266 .config_ctl_hi_val = 0x00002261,
267 .config_ctl_hi1_val = 0x2a9a699c,
268 .test_ctl_val = 0x00000000,
269 .test_ctl_hi_val = 0x00000000,
270 .test_ctl_hi1_val = 0x01800000,
271 .user_ctl_val = 0x00000100,
272 .user_ctl_hi_val = 0x00000805,
273 .user_ctl_hi1_val = 0x00000000,
277 .offset = 0x4000,
294 { 0x1, 2 },
298 .offset = 0x4000,
316 .l = 0x29,
317 .alpha = 0xaaaa,
318 .config_ctl_val = 0x20485699,
319 .config_ctl_hi_val = 0x00002261,
320 .config_ctl_hi1_val = 0x2a9a699c,
321 .test_ctl_val = 0x00000000,
322 .test_ctl_hi_val = 0x00000000,
323 .test_ctl_hi1_val = 0x01800000,
324 .user_ctl_val = 0x00000100,
325 .user_ctl_hi_val = 0x00000805,
326 .user_ctl_hi1_val = 0x00000000,
330 .offset = 0x10000,
347 { 0x1, 2 },
351 .offset = 0x10000,
369 .l = 0x29,
370 .alpha = 0xaaaa,
371 .config_ctl_val = 0x20486699,
372 .config_ctl_hi_val = 0x00002261,
373 .config_ctl_hi1_val = 0x2a9a699c,
374 .test_ctl_val = 0x00000000,
375 .test_ctl_hi_val = 0x00000000,
376 .test_ctl_hi1_val = 0x01800000,
377 .user_ctl_val = 0x00000100,
378 .user_ctl_hi_val = 0x00000805,
379 .user_ctl_hi1_val = 0x00000000,
383 .offset = 0x11000,
400 { 0x1, 2 },
404 .offset = 0x11000,
422 .l = 0x32,
423 .alpha = 0x0,
424 .config_ctl_val = 0x20485699,
425 .config_ctl_hi_val = 0x00002261,
426 .config_ctl_hi1_val = 0x2a9a699c,
427 .test_ctl_val = 0x00000000,
428 .test_ctl_hi_val = 0x00000000,
429 .test_ctl_hi1_val = 0x01800000,
430 .user_ctl_val = 0x00003100,
431 .user_ctl_hi_val = 0x00000805,
432 .user_ctl_hi1_val = 0x00000000,
436 .offset = 0x12000,
453 { 0x1, 2 },
457 .offset = 0x12000,
475 { 0x3, 3 },
479 .offset = 0x12000,
497 { P_BI_TCXO, 0 },
513 { P_BI_TCXO, 0 },
525 { P_BI_TCXO, 0 },
543 { P_BI_TCXO, 0 },
561 { P_BI_TCXO, 0 },
571 { P_BI_TCXO, 0 },
581 { P_BI_TCXO, 0 },
591 { P_BI_TCXO, 0 },
601 { P_BI_TCXO, 0 },
611 { P_SLEEP_CLK, 0 },
619 { P_BI_TCXO, 0 },
627 F(19200000, P_BI_TCXO, 1, 0, 0),
628 F(200000000, P_CAMCC_PLL0_OUT_ODD, 2, 0, 0),
629 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
630 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),
631 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
632 F(760000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
636 .cmd_rcgr = 0x7010,
637 .mnd_width = 0,
651 F(19200000, P_BI_TCXO, 1, 0, 0),
652 F(150000000, P_CAMCC_PLL0_OUT_EVEN, 4, 0, 0),
653 F(266666667, P_CAMCC_PLL0_OUT_ODD, 1.5, 0, 0),
654 F(320000000, P_CAMCC_PLL7_OUT_ODD, 1, 0, 0),
655 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
656 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),
660 .cmd_rcgr = 0xc170,
661 .mnd_width = 0,
674 F(19200000, P_BI_TCXO, 1, 0, 0),
675 F(37500000, P_CAMCC_PLL0_OUT_EVEN, 16, 0, 0),
679 .cmd_rcgr = 0xc108,
693 .cmd_rcgr = 0xc124,
707 .cmd_rcgr = 0xc204,
721 .cmd_rcgr = 0xc220,
735 F(19200000, P_BI_TCXO, 1, 0, 0),
736 F(240000000, P_CAMCC_PLL0_OUT_EVEN, 2.5, 0, 0),
737 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
741 .cmd_rcgr = 0xa064,
742 .mnd_width = 0,
755 F(19200000, P_BI_TCXO, 1, 0, 0),
756 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
760 .cmd_rcgr = 0x6004,
761 .mnd_width = 0,
774 .cmd_rcgr = 0x6028,
775 .mnd_width = 0,
788 .cmd_rcgr = 0x604c,
789 .mnd_width = 0,
802 .cmd_rcgr = 0x6074,
803 .mnd_width = 0,
816 F(19200000, P_BI_TCXO, 1, 0, 0),
817 F(100000000, P_CAMCC_PLL0_OUT_EVEN, 6, 0, 0),
818 F(200000000, P_CAMCC_PLL0_OUT_EVEN, 3, 0, 0),
819 F(300000000, P_CAMCC_PLL0_OUT_MAIN, 4, 0, 0),
820 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
824 .cmd_rcgr = 0x703c,
825 .mnd_width = 0,
838 F(19200000, P_BI_TCXO, 1, 0, 0),
839 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
840 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
844 .cmd_rcgr = 0xc0b8,
845 .mnd_width = 0,
858 F(19200000, P_BI_TCXO, 1, 0, 0),
859 F(400000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
860 F(558000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
861 F(637000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
862 F(760000000, P_CAMCC_PLL3_OUT_EVEN, 1, 0, 0),
866 .cmd_rcgr = 0xa010,
867 .mnd_width = 0,
881 F(19200000, P_BI_TCXO, 1, 0, 0),
882 F(75000000, P_CAMCC_PLL0_OUT_EVEN, 8, 0, 0),
883 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
884 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),
885 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
889 .cmd_rcgr = 0xa03c,
890 .mnd_width = 0,
903 F(19200000, P_BI_TCXO, 1, 0, 0),
904 F(400000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
905 F(558000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
906 F(637000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
907 F(760000000, P_CAMCC_PLL4_OUT_EVEN, 1, 0, 0),
911 .cmd_rcgr = 0xb010,
912 .mnd_width = 0,
926 .cmd_rcgr = 0xb03c,
927 .mnd_width = 0,
940 F(400000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0),
941 F(558000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0),
942 F(637000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0),
943 F(760000000, P_CAMCC_PLL5_OUT_EVEN, 1, 0, 0),
947 .cmd_rcgr = 0xf010,
948 .mnd_width = 0,
962 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
963 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),
964 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
968 .cmd_rcgr = 0xf03c,
969 .mnd_width = 0,
982 F(19200000, P_BI_TCXO, 1, 0, 0),
983 F(400000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0),
984 F(558000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0),
985 F(637000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0),
986 F(760000000, P_CAMCC_PLL6_OUT_EVEN, 1, 0, 0),
990 .cmd_rcgr = 0xf07c,
991 .mnd_width = 0,
1005 .cmd_rcgr = 0xf0a8,
1006 .mnd_width = 0,
1019 F(320000000, P_CAMCC_PLL7_OUT_ODD, 1, 0, 0),
1020 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
1021 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),
1022 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
1026 .cmd_rcgr = 0xc004,
1027 .mnd_width = 0,
1040 .cmd_rcgr = 0xc020,
1041 .mnd_width = 0,
1054 .cmd_rcgr = 0xc048,
1055 .mnd_width = 0,
1068 .cmd_rcgr = 0xc064,
1069 .mnd_width = 0,
1082 .cmd_rcgr = 0xc240,
1083 .mnd_width = 0,
1096 .cmd_rcgr = 0xc25c,
1097 .mnd_width = 0,
1110 .cmd_rcgr = 0xc284,
1111 .mnd_width = 0,
1124 .cmd_rcgr = 0xc2a0,
1125 .mnd_width = 0,
1138 F(19200000, P_BI_TCXO, 1, 0, 0),
1139 F(320000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
1140 F(475000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
1141 F(520000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
1142 F(600000000, P_CAMCC_PLL1_OUT_EVEN, 1, 0, 0),
1146 .cmd_rcgr = 0x8010,
1147 .mnd_width = 0,
1161 F(19200000, P_BI_TCXO, 1, 0, 0),
1162 F(200000000, P_CAMCC_PLL0_OUT_ODD, 2, 0, 0),
1163 F(400000000, P_CAMCC_PLL0_OUT_ODD, 1, 0, 0),
1164 F(480000000, P_CAMCC_PLL7_OUT_EVEN, 1, 0, 0),
1165 F(600000000, P_CAMCC_PLL0_OUT_MAIN, 2, 0, 0),
1169 .cmd_rcgr = 0xc08c,
1170 .mnd_width = 0,
1183 F(240000000, P_CAMCC_PLL7_OUT_EVEN, 2, 0, 0),
1184 F(300000000, P_CAMCC_PLL0_OUT_EVEN, 2, 0, 0),
1185 F(320000000, P_CAMCC_PLL7_OUT_ODD, 1, 0, 0),
1186 F(400000000, P_CAMCC_PLL0_OUT_MAIN, 3, 0, 0),
1190 .cmd_rcgr = 0xc144,
1191 .mnd_width = 0,
1204 F(19200000, P_BI_TCXO, 1, 0, 0),
1206 F(64000000, P_CAMCC_PLL2_OUT_EARLY, 15, 0, 0),
1210 .cmd_rcgr = 0x5004,
1224 .cmd_rcgr = 0x5024,
1238 .cmd_rcgr = 0x5044,
1252 .cmd_rcgr = 0x5064,
1266 .cmd_rcgr = 0x5084,
1280 .cmd_rcgr = 0x50a4,
1294 .cmd_rcgr = 0x50c4,
1308 .cmd_rcgr = 0x50e4,
1322 F(32000, P_SLEEP_CLK, 1, 0, 0),
1326 .cmd_rcgr = 0xc1e8,
1327 .mnd_width = 0,
1340 F(19200000, P_BI_TCXO, 1, 0, 0),
1341 F(80000000, P_CAMCC_PLL7_OUT_EVEN, 6, 0, 0),
1345 .cmd_rcgr = 0x7058,
1359 F(19200000, P_BI_TCXO, 1, 0, 0),
1363 .cmd_rcgr = 0xc1cc,
1364 .mnd_width = 0,
1377 .halt_reg = 0x7070,
1380 .enable_reg = 0x7070,
1381 .enable_mask = BIT(0),
1395 .halt_reg = 0x7054,
1398 .enable_reg = 0x7054,
1399 .enable_mask = BIT(0),
1413 .halt_reg = 0x7038,
1416 .enable_reg = 0x7038,
1417 .enable_mask = BIT(0),
1431 .halt_reg = 0x7028,
1434 .enable_reg = 0x7028,
1435 .enable_mask = BIT(0),
1449 .halt_reg = 0xc18c,
1452 .enable_reg = 0xc18c,
1453 .enable_mask = BIT(0),
1467 .halt_reg = 0xc194,
1470 .enable_reg = 0xc194,
1471 .enable_mask = BIT(0),
1485 .halt_reg = 0xc120,
1488 .enable_reg = 0xc120,
1489 .enable_mask = BIT(0),
1503 .halt_reg = 0xc13c,
1506 .enable_reg = 0xc13c,
1507 .enable_mask = BIT(0),
1521 .halt_reg = 0xc21c,
1524 .enable_reg = 0xc21c,
1525 .enable_mask = BIT(0),
1539 .halt_reg = 0xc238,
1542 .enable_reg = 0xc238,
1543 .enable_mask = BIT(0),
1557 .halt_reg = 0xc1c8,
1560 .enable_reg = 0xc1c8,
1561 .enable_mask = BIT(0),
1575 .halt_reg = 0xc168,
1578 .enable_reg = 0xc168,
1579 .enable_mask = BIT(0),
1593 .halt_reg = 0x601c,
1596 .enable_reg = 0x601c,
1597 .enable_mask = BIT(0),
1611 .halt_reg = 0x6040,
1614 .enable_reg = 0x6040,
1615 .enable_mask = BIT(0),
1629 .halt_reg = 0x6064,
1632 .enable_reg = 0x6064,
1633 .enable_mask = BIT(0),
1647 .halt_reg = 0x608c,
1650 .enable_reg = 0x608c,
1651 .enable_mask = BIT(0),
1665 .halt_reg = 0x6020,
1668 .enable_reg = 0x6020,
1669 .enable_mask = BIT(0),
1683 .halt_reg = 0x6044,
1686 .enable_reg = 0x6044,
1687 .enable_mask = BIT(0),
1701 .halt_reg = 0x6068,
1704 .enable_reg = 0x6068,
1705 .enable_mask = BIT(0),
1719 .halt_reg = 0x6090,
1722 .enable_reg = 0x6090,
1723 .enable_mask = BIT(0),
1737 .halt_reg = 0xc1e4,
1740 .enable_reg = 0xc1e4,
1741 .enable_mask = BIT(0),
1755 .halt_reg = 0xc0d8,
1758 .enable_reg = 0xc0d8,
1759 .enable_mask = BIT(0),
1773 .halt_reg = 0xc0d0,
1776 .enable_reg = 0xc0d0,
1777 .enable_mask = BIT(0),
1791 .halt_reg = 0xa080,
1794 .enable_reg = 0xa080,
1795 .enable_mask = BIT(0),
1809 .halt_reg = 0xa028,
1812 .enable_reg = 0xa028,
1813 .enable_mask = BIT(0),
1827 .halt_reg = 0xa07c,
1830 .enable_reg = 0xa07c,
1831 .enable_mask = BIT(0),
1845 .halt_reg = 0xa054,
1848 .enable_reg = 0xa054,
1849 .enable_mask = BIT(0),
1863 .halt_reg = 0xa038,
1866 .enable_reg = 0xa038,
1867 .enable_mask = BIT(0),
1881 .halt_reg = 0xb068,
1884 .enable_reg = 0xb068,
1885 .enable_mask = BIT(0),
1899 .halt_reg = 0xb028,
1902 .enable_reg = 0xb028,
1903 .enable_mask = BIT(0),
1917 .halt_reg = 0xb064,
1920 .enable_reg = 0xb064,
1921 .enable_mask = BIT(0),
1935 .halt_reg = 0xb054,
1938 .enable_reg = 0xb054,
1939 .enable_mask = BIT(0),
1953 .halt_reg = 0xb038,
1956 .enable_reg = 0xb038,
1957 .enable_mask = BIT(0),
1971 .halt_reg = 0xf068,
1974 .enable_reg = 0xf068,
1975 .enable_mask = BIT(0),
1989 .halt_reg = 0xf028,
1992 .enable_reg = 0xf028,
1993 .enable_mask = BIT(0),
2007 .halt_reg = 0xf064,
2010 .enable_reg = 0xf064,
2011 .enable_mask = BIT(0),
2025 .halt_reg = 0xf054,
2028 .enable_reg = 0xf054,
2029 .enable_mask = BIT(0),
2043 .halt_reg = 0xf038,
2046 .enable_reg = 0xf038,
2047 .enable_mask = BIT(0),
2061 .halt_reg = 0xf0d4,
2064 .enable_reg = 0xf0d4,
2065 .enable_mask = BIT(0),
2079 .halt_reg = 0xf094,
2082 .enable_reg = 0xf094,
2083 .enable_mask = BIT(0),
2097 .halt_reg = 0xf0d0,
2100 .enable_reg = 0xf0d0,
2101 .enable_mask = BIT(0),
2115 .halt_reg = 0xf0c0,
2118 .enable_reg = 0xf0c0,
2119 .enable_mask = BIT(0),
2133 .halt_reg = 0xf0a4,
2136 .enable_reg = 0xf0a4,
2137 .enable_mask = BIT(0),
2151 .halt_reg = 0xc01c,
2154 .enable_reg = 0xc01c,
2155 .enable_mask = BIT(0),
2169 .halt_reg = 0xc040,
2172 .enable_reg = 0xc040,
2173 .enable_mask = BIT(0),
2187 .halt_reg = 0xc038,
2190 .enable_reg = 0xc038,
2191 .enable_mask = BIT(0),
2205 .halt_reg = 0xc060,
2208 .enable_reg = 0xc060,
2209 .enable_mask = BIT(0),
2223 .halt_reg = 0xc084,
2226 .enable_reg = 0xc084,
2227 .enable_mask = BIT(0),
2241 .halt_reg = 0xc07c,
2244 .enable_reg = 0xc07c,
2245 .enable_mask = BIT(0),
2259 .halt_reg = 0xc258,
2262 .enable_reg = 0xc258,
2263 .enable_mask = BIT(0),
2277 .halt_reg = 0xc27c,
2280 .enable_reg = 0xc27c,
2281 .enable_mask = BIT(0),
2295 .halt_reg = 0xc274,
2298 .enable_reg = 0xc274,
2299 .enable_mask = BIT(0),
2313 .halt_reg = 0xc29c,
2316 .enable_reg = 0xc29c,
2317 .enable_mask = BIT(0),
2331 .halt_reg = 0xc2c0,
2334 .enable_reg = 0xc2c0,
2335 .enable_mask = BIT(0),
2349 .halt_reg = 0xc2b8,
2352 .enable_reg = 0xc2b8,
2353 .enable_mask = BIT(0),
2367 .halt_reg = 0x8040,
2370 .enable_reg = 0x8040,
2371 .enable_mask = BIT(0),
2385 .halt_reg = 0x803c,
2388 .enable_reg = 0x803c,
2389 .enable_mask = BIT(0),
2403 .halt_reg = 0x8038,
2406 .enable_reg = 0x8038,
2407 .enable_mask = BIT(0),
2421 .halt_reg = 0x8028,
2424 .enable_reg = 0x8028,
2425 .enable_mask = BIT(0),
2439 .halt_reg = 0x9028,
2442 .enable_reg = 0x9028,
2443 .enable_mask = BIT(0),
2457 .halt_reg = 0x9024,
2460 .enable_reg = 0x9024,
2461 .enable_mask = BIT(0),
2475 .halt_reg = 0x9020,
2478 .enable_reg = 0x9020,
2479 .enable_mask = BIT(0),
2493 .halt_reg = 0x9010,
2496 .enable_reg = 0x9010,
2497 .enable_mask = BIT(0),
2511 .halt_reg = 0xc0a4,
2514 .enable_reg = 0xc0a4,
2515 .enable_mask = BIT(0),
2529 .halt_reg = 0xc15c,
2532 .enable_reg = 0xc15c,
2533 .enable_mask = BIT(0),
2547 .halt_reg = 0x501c,
2550 .enable_reg = 0x501c,
2551 .enable_mask = BIT(0),
2565 .halt_reg = 0x503c,
2568 .enable_reg = 0x503c,
2569 .enable_mask = BIT(0),
2583 .halt_reg = 0x505c,
2586 .enable_reg = 0x505c,
2587 .enable_mask = BIT(0),
2601 .halt_reg = 0x507c,
2604 .enable_reg = 0x507c,
2605 .enable_mask = BIT(0),
2619 .halt_reg = 0x509c,
2622 .enable_reg = 0x509c,
2623 .enable_mask = BIT(0),
2637 .halt_reg = 0x50bc,
2640 .enable_reg = 0x50bc,
2641 .enable_mask = BIT(0),
2655 .halt_reg = 0x50dc,
2658 .enable_reg = 0x50dc,
2659 .enable_mask = BIT(0),
2673 .halt_reg = 0x50fc,
2676 .enable_reg = 0x50fc,
2677 .enable_mask = BIT(0),
2691 .halt_reg = 0xc200,
2694 .enable_reg = 0xc200,
2695 .enable_mask = BIT(0),
2711 .gdscr = 0x7004,
2721 .gdscr = 0xa004,
2731 .gdscr = 0xb004,
2741 .gdscr = 0xf004,
2751 .gdscr = 0xf070,
2761 .gdscr = 0x8004,
2771 .gdscr = 0x9004,
2781 .gdscr = 0xc1bc,
2938 [CAMCC_BPS_BCR] = { 0x7000 },
2939 [CAMCC_CAMNOC_BCR] = { 0xc16c },
2940 [CAMCC_CCI_BCR] = { 0xc104 },
2941 [CAMCC_CPAS_BCR] = { 0xc164 },
2942 [CAMCC_CSI0PHY_BCR] = { 0x6000 },
2943 [CAMCC_CSI1PHY_BCR] = { 0x6024 },
2944 [CAMCC_CSI2PHY_BCR] = { 0x6048 },
2945 [CAMCC_CSI3PHY_BCR] = { 0x6070 },
2946 [CAMCC_ICP_BCR] = { 0xc0b4 },
2947 [CAMCC_IFE_0_BCR] = { 0xa000 },
2948 [CAMCC_IFE_1_BCR] = { 0xb000 },
2949 [CAMCC_IFE_2_BCR] = { 0xf000 },
2950 [CAMCC_IFE_3_BCR] = { 0xf06c },
2951 [CAMCC_IFE_LITE_0_BCR] = { 0xc000 },
2952 [CAMCC_IFE_LITE_1_BCR] = { 0xc044 },
2953 [CAMCC_IFE_LITE_2_BCR] = { 0xc23c },
2954 [CAMCC_IFE_LITE_3_BCR] = { 0xc280 },
2955 [CAMCC_IPE_0_BCR] = { 0x8000 },
2956 [CAMCC_IPE_1_BCR] = { 0x9000 },
2957 [CAMCC_JPEG_BCR] = { 0xc088 },
2958 [CAMCC_LRME_BCR] = { 0xc140 },
2965 .max_register = 0x13020,
3016 regmap_update_bits(regmap, 0xc1e4, BIT(0), 1); in camcc_sc8280xp_probe()
3024 return 0; in camcc_sc8280xp_probe()
3027 regmap_update_bits(regmap, 0xc1e4, BIT(0), 0); in camcc_sc8280xp_probe()