Lines Matching +full:m +full:- +full:ahb
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
8 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/microchip,mpfs-clock.h>
99 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; in mpfs_clk_msspll_recalc_rate()
100 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; in mpfs_clk_msspll_recalc_rate()
101 void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; in mpfs_clk_msspll_recalc_rate()
117 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; in mpfs_clk_msspll_round_rate()
118 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; in mpfs_clk_msspll_round_rate()
130 msspll_hw->flags); in mpfs_clk_msspll_round_rate()
136 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; in mpfs_clk_msspll_set_rate()
137 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; in mpfs_clk_msspll_set_rate()
138 void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; in mpfs_clk_msspll_set_rate()
150 msspll_hw->flags); in mpfs_clk_msspll_set_rate()
195 msspll_hw->base = data->msspll_base; in mpfs_clk_register_mssplls()
196 ret = devm_clk_hw_register(dev, &msspll_hw->hw); in mpfs_clk_register_mssplls()
201 data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw; in mpfs_clk_register_mssplls()
255 cfg_hw->cfg.reg = data->base + cfg_hw->reg_offset; in mpfs_clk_register_cfgs()
256 ret = devm_clk_hw_register(dev, &cfg_hw->cfg.hw); in mpfs_clk_register_cfgs()
259 cfg_hw->id); in mpfs_clk_register_cfgs()
261 id = cfg_hw->id; in mpfs_clk_register_cfgs()
262 data->hw_data.hws[id] = &cfg_hw->cfg.hw; in mpfs_clk_register_cfgs()
269 * peripheral clocks - devices connected to axi or ahb buses.
284 * - CLK_ENVM: reserved by hart software services (hss) superloop monitor/m mode interrupt
286 * - CLK_MMUART0: reserved by the hss
287 * - CLK_DDRC: provides clock to the ddr subsystem
288 * - CLK_RTC: the onboard RTC's AHB bus clock must be kept running as the rtc will stop
289 * if the AHB interface clock is disabled
290 * - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric InterConnect)
293 * - CLK_ATHENA: The athena clock is FIC4, which is reserved for the Athena TeraFire.
297 CLK_PERIPH(CLK_ENVM, "clk_periph_envm", PARENT_CLK(AHB), 0, CLK_IS_CRITICAL),
298 CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", PARENT_CLK(AHB), 1, 0),
299 CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0),
300 CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0),
302 CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL),
303 CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0),
304 CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0),
305 CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", PARENT_CLK(AHB), 8, 0),
306 CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", PARENT_CLK(AHB), 9, 0),
307 CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", PARENT_CLK(AHB), 10, 0),
308 CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", PARENT_CLK(AHB), 11, 0),
309 CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", PARENT_CLK(AHB), 12, 0),
310 CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", PARENT_CLK(AHB), 13, 0),
311 CLK_PERIPH(CLK_CAN0, "clk_periph_can0", PARENT_CLK(AHB), 14, 0),
312 CLK_PERIPH(CLK_CAN1, "clk_periph_can1", PARENT_CLK(AHB), 15, 0),
313 CLK_PERIPH(CLK_USB, "clk_periph_usb", PARENT_CLK(AHB), 16, 0),
314 CLK_PERIPH(CLK_RTC, "clk_periph_rtc", PARENT_CLK(AHB), 18, CLK_IS_CRITICAL),
315 CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", PARENT_CLK(AHB), 19, 0),
316 CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", PARENT_CLK(AHB), 20, 0),
317 CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", PARENT_CLK(AHB), 21, 0),
318 CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", PARENT_CLK(AHB), 22, 0),
319 CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", PARENT_CLK(AHB), 23, CLK_IS_CRITICAL),
325 CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0),
337 periph_hw->periph.reg = data->base + REG_SUBBLK_CLOCK_CR; in mpfs_clk_register_periphs()
338 ret = devm_clk_hw_register(dev, &periph_hw->periph.hw); in mpfs_clk_register_periphs()
341 periph_hw->id); in mpfs_clk_register_periphs()
344 data->hw_data.hws[id] = &periph_hw->periph.hw; in mpfs_clk_register_periphs()
358 struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); in mpfs_reset_read()
360 return readl_relaxed(clock_data->base + REG_SUBBLK_RESET_CR); in mpfs_reset_read()
366 struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent); in mpfs_reset_write()
368 writel_relaxed(val, clock_data->base + REG_SUBBLK_RESET_CR); in mpfs_reset_write()
394 return ERR_PTR(-ENOMEM); in mpfs_reset_adev_alloc()
396 adev->name = "reset-mpfs"; in mpfs_reset_adev_alloc()
397 adev->dev.parent = clk_data->dev; in mpfs_reset_adev_alloc()
398 adev->dev.release = mpfs_reset_adev_release; in mpfs_reset_adev_alloc()
399 adev->id = 666u; in mpfs_reset_adev_alloc()
425 return devm_add_action_or_reset(clk_data->dev, mpfs_reset_unregister_adev, adev); in mpfs_reset_controller_register()
439 struct device *dev = &pdev->dev; in mpfs_clk_probe()
450 return -ENOMEM; in mpfs_clk_probe()
452 clk_data->base = devm_platform_ioremap_resource(pdev, 0); in mpfs_clk_probe()
453 if (IS_ERR(clk_data->base)) in mpfs_clk_probe()
454 return PTR_ERR(clk_data->base); in mpfs_clk_probe()
456 clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1); in mpfs_clk_probe()
457 if (IS_ERR(clk_data->msspll_base)) in mpfs_clk_probe()
458 return PTR_ERR(clk_data->msspll_base); in mpfs_clk_probe()
460 clk_data->hw_data.num = num_clks; in mpfs_clk_probe()
461 clk_data->dev = dev; in mpfs_clk_probe()
478 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data); in mpfs_clk_probe()
486 { .compatible = "microchip,mpfs-clkcfg", },
494 .name = "microchip-mpfs-clkcfg",