Lines Matching +full:reg +full:- +full:names
1 // SPDX-License-Identifier: GPL-2.0+
3 * Amlogic Meson-G12A Clock Controller Driver
13 #include <linux/clk-provider.h>
20 #include "clk-mpll.h"
21 #include "clk-pll.h"
22 #include "clk-regmap.h"
23 #include "clk-cpu-dyndiv.h"
24 #include "vid-pll-div.h"
25 #include "meson-eeclk.h"
28 #include <dt-bindings/clock/g12a-clkc.h>
311 * b) CCF has a clock hand-off mechanism to make the sure the
347 * b) CCF has a clock hand-off mechanism to make the sure the
354 /* Datasheet names this field as "premux0" */
375 /* Datasheet names this field as "premux1" */
391 /* This sub-tree is used a parking clock */
396 /* Datasheet names this field as "mux0_divn_tcnt" */
421 /* Datasheet names this field as "postmux0" */
441 /* Datasheet names this field as "Mux1_divn_tcnt" */
458 /* Datasheet names this field as "postmux1" */
473 /* This sub-tree is used a parking clock */
478 /* Datasheet names this field as "Final_dyn_mux_sel" */
498 /* Datasheet names this field as "Final_mux_sel" */
518 /* Datasheet names this field as "Final_mux_sel" */
538 /* Datasheet names this field as "premux0" */
559 /* Datasheet names this field as "mux0_divn_tcnt" */
584 /* Datasheet names this field as "postmux0" */
604 /* Datasheet names this field as "premux1" */
620 /* This sub-tree is used a parking clock */
625 /* Datasheet names this field as "Mux1_divn_tcnt" */
642 /* Datasheet names this field as "postmux1" */
657 /* This sub-tree is used a parking clock */
662 /* Datasheet names this field as "Final_dyn_mux_sel" */
682 /* Datasheet names this field as "Final_mux_sel" */
704 /* Datasheet names this field as "premux0" */
724 /* Datasheet names this field as "premux1" */
744 /* Datasheet names this field as "Mux0_divn_tcnt" */
761 /* Datasheet names this field as "postmux0" */
779 /* Datasheet names this field as "Mux1_divn_tcnt" */
796 /* Datasheet names this field as "postmux1" */
814 /* Datasheet names this field as "Final_dyn_mux_sel" */
832 /* Datasheet names this field as "Final_mux_sel" */
850 /* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 0 */
868 /* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 1 */
886 /* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 2 */
904 /* Datasheet names this field as "Cpu_clk_sync_mux_sel" bit 4 */
959 * \- cpu_clk_dyn in g12a_cpu_clk_postmux_notifier_cb()
960 * \- cpu_clk_postmux0 in g12a_cpu_clk_postmux_notifier_cb()
961 * \- cpu_clk_muxX_div in g12a_cpu_clk_postmux_notifier_cb()
962 * \- cpu_clk_premux0 in g12a_cpu_clk_postmux_notifier_cb()
963 * \- fclk_div3 or fclk_div2 in g12a_cpu_clk_postmux_notifier_cb()
965 * \- cpu_clk_premux0 in g12a_cpu_clk_postmux_notifier_cb()
966 * \- fclk_div3 or fclk_div2 in g12a_cpu_clk_postmux_notifier_cb()
970 clk_hw_set_parent(nb_data->cpu_clk_premux1, in g12a_cpu_clk_postmux_notifier_cb()
971 nb_data->xtal); in g12a_cpu_clk_postmux_notifier_cb()
974 clk_hw_set_parent(nb_data->cpu_clk_postmux1, in g12a_cpu_clk_postmux_notifier_cb()
975 nb_data->cpu_clk_premux1); in g12a_cpu_clk_postmux_notifier_cb()
978 clk_hw_set_parent(nb_data->cpu_clk_dyn, in g12a_cpu_clk_postmux_notifier_cb()
979 nb_data->cpu_clk_postmux1); in g12a_cpu_clk_postmux_notifier_cb()
984 * \- cpu_clk_dyn in g12a_cpu_clk_postmux_notifier_cb()
985 * \- cpu_clk_postmux1 in g12a_cpu_clk_postmux_notifier_cb()
986 * \- cpu_clk_premux1 in g12a_cpu_clk_postmux_notifier_cb()
987 * \- xtal in g12a_cpu_clk_postmux_notifier_cb()
1002 clk_hw_set_parent(nb_data->cpu_clk_dyn, in g12a_cpu_clk_postmux_notifier_cb()
1003 nb_data->cpu_clk_postmux0); in g12a_cpu_clk_postmux_notifier_cb()
1008 * \- cpu_clk_dyn in g12a_cpu_clk_postmux_notifier_cb()
1009 * \- cpu_clk_postmux0 in g12a_cpu_clk_postmux_notifier_cb()
1010 * \- cpu_clk_muxX_div in g12a_cpu_clk_postmux_notifier_cb()
1011 * \- cpu_clk_premux0 in g12a_cpu_clk_postmux_notifier_cb()
1012 * \- fclk_div3 or fclk_div2 in g12a_cpu_clk_postmux_notifier_cb()
1014 * \- cpu_clk_premux0 in g12a_cpu_clk_postmux_notifier_cb()
1015 * \- fclk_div3 or fclk_div2 in g12a_cpu_clk_postmux_notifier_cb()
1062 * \- sys_pll in g12a_sys_pll_notifier_cb()
1063 * \- sys_pll_dco in g12a_sys_pll_notifier_cb()
1067 clk_hw_set_parent(nb_data->cpu_clk, in g12a_sys_pll_notifier_cb()
1068 nb_data->cpu_clk_dyn); in g12a_sys_pll_notifier_cb()
1073 * \- cpu_clk_dyn in g12a_sys_pll_notifier_cb()
1074 * \- cpu_clk_dynX in g12a_sys_pll_notifier_cb()
1075 * \- cpu_clk_dynX_sel in g12a_sys_pll_notifier_cb()
1076 * \- cpu_clk_dynX_div in g12a_sys_pll_notifier_cb()
1077 * \- xtal/fclk_div2/fclk_div3 in g12a_sys_pll_notifier_cb()
1078 * \- xtal/fclk_div2/fclk_div3 in g12a_sys_pll_notifier_cb()
1092 clk_hw_set_parent(nb_data->cpu_clk, in g12a_sys_pll_notifier_cb()
1093 nb_data->sys_pll); in g12a_sys_pll_notifier_cb()
1099 * \- sys_pll in g12a_sys_pll_notifier_cb()
1100 * \- sys_pll_dco in g12a_sys_pll_notifier_cb()
1318 .index = -1,
1616 { .reg = HHI_GP0_PLL_CNTL1, .def = 0x00000000 },
1617 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x00000000 },
1618 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x48681c00 },
1619 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x33771290 },
1620 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x39272000 },
1621 { .reg = HHI_GP0_PLL_CNTL6, .def = 0x56540000 },
1756 { .reg = HHI_HIFI_PLL_CNTL1, .def = 0x00000000 },
1757 { .reg = HHI_HIFI_PLL_CNTL2, .def = 0x00000000 },
1758 { .reg = HHI_HIFI_PLL_CNTL3, .def = 0x6a285c00 },
1759 { .reg = HHI_HIFI_PLL_CNTL4, .def = 0x65771290 },
1760 { .reg = HHI_HIFI_PLL_CNTL5, .def = 0x39272000 },
1761 { .reg = HHI_HIFI_PLL_CNTL6, .def = 0x56540000 },
1836 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x20090496 },
1837 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x30090496 },
1838 { .reg = HHI_PCIE_PLL_CNTL1, .def = 0x00000000 },
1839 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001100 },
1840 { .reg = HHI_PCIE_PLL_CNTL3, .def = 0x10058e00 },
1841 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x000100c0 },
1842 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000048 },
1843 { .reg = HHI_PCIE_PLL_CNTL5, .def = 0x68000068, .delay_us = 20 },
1844 { .reg = HHI_PCIE_PLL_CNTL4, .def = 0x008100c0, .delay_us = 10 },
1845 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x34090496 },
1846 { .reg = HHI_PCIE_PLL_CNTL0, .def = 0x14090496, .delay_us = 10 },
1847 { .reg = HHI_PCIE_PLL_CNTL2, .def = 0x00001000 },
2202 { .reg = HHI_MPLL_CNTL2, .def = 0x40000033 },
2256 { .reg = HHI_MPLL_CNTL4, .def = 0x40000033 },
2310 { .reg = HHI_MPLL_CNTL6, .def = 0x40000033 },
2364 { .reg = HHI_MPLL_CNTL8, .def = 0x40000033 },
3873 * muxed by a glitch-free switch. The CCF can manage this glitch-free
3874 * mux because it does top-to-bottom updates the each clock tree and
5342 { .reg = HHI_MPLL_CNTL0, .def = 0x00000543 },
5383 struct device *dev = &pdev->dev; in meson_g12b_dvfs_setup()
5460 struct device *dev = &pdev->dev; in meson_g12a_dvfs_setup()
5500 eeclkc_data = of_device_get_match_data(&pdev->dev); in meson_g12a_probe()
5502 return -EINVAL; in meson_g12a_probe()
5511 if (g12a_data->dvfs_setup) in meson_g12a_probe()
5512 return g12a_data->dvfs_setup(pdev); in meson_g12a_probe()
5557 .compatible = "amlogic,g12a-clkc",
5561 .compatible = "amlogic,g12b-clkc",
5565 .compatible = "amlogic,sm1-clkc",
5575 .name = "g12a-clkc",