habanalabs/gaudi2/gaudi2P.h

1 /* SPDX-License-Identifier: GPL-2.0
3  * Copyright 2020-2022 HabanaLabs, Ltd.
19 #define GAUDI2_LINUX_FW_FILE	"habanalabs/gaudi2/gaudi2-fit.itb"
20 #define GAUDI2_BOOT_FIT_FILE	"habanalabs/gaudi2/gaudi2-boot-fit.itb"
46 	(((mmDCORE0_SYNC_MNGR_OBJS_SOB_OBJ_8191 - \
50 	(((mmDCORE0_SYNC_MNGR_OBJS_MON_STATUS_2047 - \
58 #define NUM_OF_EXPOSED_SM_BLOCKS	((NUM_OF_DCORES - 1) * 2)
75 #define SM_OBJS_BLOCK_SIZE		(mmDCORE0_SYNC_MNGR_OBJS_SM_SEC_0 - \
107 	(GAUDI2_DCORE1_ENGINE_ID_EDMA_0 - GAUDI2_DCORE0_ENGINE_ID_EDMA_0)
142 #define VA_HOST_SPACE_PAGE_SIZE		(VA_HOST_SPACE_PAGE_END - VA_HOST_SPACE_PAGE_START)
145 #define VA_HOST_SPACE_HPAGE_SIZE	(VA_HOST_SPACE_HPAGE_END - VA_HOST_SPACE_HPAGE_START)
157  * address space which is determined at run-time.
217 /* RAZWI initiator coordinates- X- 5 bits, Y- 4 bits */
237 #define HW_CAP_NIC_MASK			GENMASK_ULL(NIC_NUMBER_OF_ENGINES - 1, 0)
244 #define GAUDI2_NUM_TESTED_QS (GAUDI2_QUEUE_ID_CPU_PQ - GAUDI2_QUEUE_ID_PDMA_0_0)
251 			GAUDI2_RESERVED_SOB_CS_COMPLETION_FIRST + GAUDI2_MAX_PENDING_CS - 1,
255 			GAUDI2_RESERVED_SOB_DEC_NRM_FIRST + NUMBER_OF_DEC - 1,
258 			GAUDI2_RESERVED_SOB_DEC_ABNRM_FIRST + NUMBER_OF_DEC - 1,
265 			GAUDI2_RESERVED_MON_CS_COMPLETION_FIRST + GAUDI2_MAX_PENDING_CS - 1,
269 			GAUDI2_RESERVED_MON_DEC_NRM_FIRST + 3 * NUMBER_OF_DEC - 1,
272 			GAUDI2_RESERVED_MON_DEC_ABNRM_FIRST + 3 * NUMBER_OF_DEC - 1,
284  * At most- two faulty TPCs are allowed
285  * First replacement to a faulty TPC will be TPC24, second- TPC23
376 /* specific EDMA enumeration */
421 	GAUDI2_IRQ_NUM_NIC_PORT_LAST = (GAUDI2_IRQ_NUM_NIC_PORT_FIRST + NIC_NUMBER_OF_PORTS - 1),
425 	GAUDI2_IRQ_NUM_RESERVED_LAST = (GAUDI2_MSIX_ENTRIES - GAUDI2_TOTAL_USER_INTERRUPTS - 1),
428 	GAUDI2_IRQ_NUM_USER_LAST = (GAUDI2_IRQ_NUM_USER_FIRST + GAUDI2_NUM_USER_INTERRUPTS - 1),
429 	GAUDI2_IRQ_NUM_LAST = (GAUDI2_MSIX_ENTRIES - 1)
435  * struct dup_block_ctx - context to initialize unit instances across multiple
439  * @instance_cfg_fn: instance specific configuration function.
444  * @enabled_mask: mask of enabled instances (1- enabled, 0- disabled).
460  * struct gaudi2_queues_test_info - Holds the address of a the messages used for testing the
471  * struct gaudi2_device - ASIC specific manage structure.
472  * @cpucp_info_get: get information on device from CPU-CP
478  *                             this memory region should be write-only.
482  * @virt_msix_db_cpu_addr: host memory page for the virtual MSI-X doorbell.
483  * @virt_msix_db_dma_addr: bus address of the page for the virtual MSI-X doorbell.
485  * @hw_cap_initialized: This field contains a bit per H/W engine. When that
486  *                      engine is initialized, that bit is set by the driver to
487  *                      signal we can use this engine in later code paths.
489  *                      engine.
490  * @active_hw_arc: This field contains a bit per ARC of an H/W engine with
491  *                 exception of TPC and NIC engines. Once an engine arc is
495  *                 of its corresponding ARC of the H/W engine.
496  * @dec_hw_cap_initialized: This field contains a bit per decoder H/W engine.
497  *                      When that engine is initialized, that bit is set by
498  *                      the driver to signal we can use this engine in later
501  *                      engine.
502  * @tpc_hw_cap_initialized: This field contains a bit per TPC H/W engine.
503  *                      When that engine is initialized, that bit is set by
504  *                      the driver to signal we can use this engine in later
507  *                      engine.
509  *                  Once an engine arc is initialized, its respective bit is
511  *                  corresponding ARC of the TPC engine.
512  * @nic_hw_cap_initialized: This field contains a bit per nic H/W engine.
514  *                  Once an engine arc is initialized, its respective bit is
516  *                  corresponding ARC of the NIC engine.
524  * @aux_ops: functions for core <-> aux drivers communication.