1 // SPDX-License-Identifier: GPL-2.0-only
17 #include <asm/nospec-branch.h>
36  *	TLB flushing, formerly SMP-only
67  * Instead we have a small per-cpu array of ASIDs and cache the last few mm's
74  * ASID  - [0, TLB_NR_DYN_ASIDS-1]
77  * kPCID - [1, TLB_NR_DYN_ASIDS]
81  * uPCID - [2048 + 1, 2048 + TLB_NR_DYN_ASIDS]
101 #define CR3_AVAIL_PCID_BITS (X86_CR3_PCID_BITS - PTI_CONSUMED_PCID_BITS)
104  * ASIDs are zero-based: 0->MAX_AVAIL_ASID are valid.  -1 below to account
105  * for them being zero-based.  Another -1 is because PCID 0 is reserved for
106  * use by non-PCID-aware users.
108 #define MAX_ASID_AVAILABLE ((1 << CR3_AVAIL_PCID_BITS) - 2)
131 	 * The dynamically-assigned ASIDs that get passed in are small  in kern_pcid()
135 	 * If PCID is on, ASID-aware code paths put the ASID+1 into the  in kern_pcid()
137 	 * situation in which PCID-unaware code saves CR3, loads some other  in kern_pcid()
139 	 * the TLB for ASID 0 if the saved ASID was nonzero.  It also means  in kern_pcid()
140 	 * that any bugs involving loading a PCID-enabled CR3 with  in kern_pcid()
185  * We get here when we do something requiring a TLB invalidation
188  * forces a TLB flush when the context is loaded.
235 		    next->context.ctx_id)  in choose_new_asid()
248 	*new_asid = this_cpu_add_return(cpu_tlbstate.next_asid, 1) - 1;  in choose_new_asid()
296 	 * that load_cr3() is serializing and orders TLB  in load_new_mm_cr3()
307 	 * It's plausible that we're in lazy TLB mode while our mm is init_mm.  in leave_mm()
308 	 * If so, our callers still expect us to flush the TLB, but there  in leave_mm()
309 	 * aren't any user TLB entries in init_mm to worry about.  in leave_mm()
335  * Invoked from return to user/guest by a task that opted-in to L1D
363 		clear_ti_thread_flag(&next->thread_info, TIF_SPEC_L1D_FLUSH);  in l1d_flush_evaluate()
364 		next->l1d_flush_kill.func = l1d_flush_force_sigbus;  in l1d_flush_evaluate()
365 		task_work_add(next, &next->l1d_flush_kill, TWA_RESUME);  in l1d_flush_evaluate()
380 	return (unsigned long)next->mm | spec_bits;  in mm_mangle_tif_spec_bits()
387 	if (!next || !next->mm)  in cond_mitigation()
396 	 * doing Spectre-v2 attacks on another.  in cond_mitigation()
400 	 * same process. Using the mm pointer instead of mm->context.ctx_id  in cond_mitigation()
423 		 * - the same user space task is scheduled out and later  in cond_mitigation()
427 		 * - a user space task belonging to the same process is  in cond_mitigation()
430 		 * - a user space task belonging to the same process is  in cond_mitigation()
453 					(unsigned long)next->mm)  in cond_mitigation()
475 	     atomic_read(&mm->context.perf_rdpmc_allowed))) {  in cr4_update_pce_mm()
509 	 * from lazy TLB mode to normal mode if active_mm isn't changing.  in switch_mm_irqs_off()
530 	if (WARN_ON_ONCE(__read_cr3() != build_cr3(real_prev->pgd, prev_asid,  in switch_mm_irqs_off()
533 		 * If we were to BUG here, we'd be very likely to kill  in switch_mm_irqs_off()
552 	 * core serialization before returning to user-space, after  in switch_mm_irqs_off()
553 	 * storing to rq->curr, when changing mm.  This is because  in switch_mm_irqs_off()
565 			   next->context.ctx_id);  in switch_mm_irqs_off()
573 		 * Even in lazy TLB mode, the CPU should stay set in the  in switch_mm_irqs_off()
574 		 * mm_cpumask. The TLB shootdown code can figure out from  in switch_mm_irqs_off()
582 		 * If the CPU is not in lazy TLB mode, we are just switching  in switch_mm_irqs_off()
584 		 * process. No TLB flush required.  in switch_mm_irqs_off()
591 		 * If the TLB is up to date, just use it.  in switch_mm_irqs_off()
593 		 * the TLB shootdown code.  in switch_mm_irqs_off()
596 		next_tlb_gen = atomic64_read(&next->context.tlb_gen);  in switch_mm_irqs_off()
602 		 * TLB contents went out of date while we were in lazy  in switch_mm_irqs_off()
603 		 * mode. Fall through to the TLB switching code below.  in switch_mm_irqs_off()
616 		 * Skip kernel threads; we never send init_mm TLB flushing IPIs,  in switch_mm_irqs_off()
630 		next_tlb_gen = atomic64_read(&next->context.tlb_gen);  in switch_mm_irqs_off()
641 		this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id);  in switch_mm_irqs_off()
643 		load_new_mm_cr3(next->pgd, new_asid, new_lam, true);  in switch_mm_irqs_off()
648 		load_new_mm_cr3(next->pgd, new_asid, new_lam, false);  in switch_mm_irqs_off()
672  * lazy tricks to try to minimize TLB flushes.
690  * - The ASID changed from what cpu_tlbstate thinks it is (most likely
694  * - The TLB contains junk in slots corresponding to inactive ASIDs.
696  * - The CPU went so far out to lunch that it may have missed a TLB
707 	WARN_ON((cr3 & CR3_ADDR_MASK) != __pa(mm->pgd));  in initialize_tlbstate_and_flush()
721 	/* Disable LAM, force ASID 0 and force a TLB flush. */  in initialize_tlbstate_and_flush()
722 	write_cr3(build_cr3(mm->pgd, 0, 0));  in initialize_tlbstate_and_flush()
728 	this_cpu_write(cpu_tlbstate.ctxs[0].ctx_id, mm->context.ctx_id);  in initialize_tlbstate_and_flush()
738  * TLB fills that happen after we flush the TLB are ordered after we
748 	 * - mm_tlb_gen:     the latest generation.  in flush_tlb_func()
749 	 * - local_tlb_gen:  the generation that this CPU has already caught  in flush_tlb_func()
751 	 * - f->new_tlb_gen: the generation that the requester of the flush  in flush_tlb_func()
758 	bool local = smp_processor_id() == f->initiating_cpu;  in flush_tlb_func()
770 		if (f->mm && f->mm != loaded_mm)  in flush_tlb_func()
778 		   loaded_mm->context.ctx_id);  in flush_tlb_func()
783 		 * paging-structure cache to avoid speculatively reading  in flush_tlb_func()
784 		 * garbage into our TLB.  Since switching to init_mm is barely  in flush_tlb_func()
788 		 * IPIs to lazy TLB mode CPUs.  in flush_tlb_func()
794 	if (unlikely(f->new_tlb_gen != TLB_GENERATION_INVALID &&  in flush_tlb_func()
795 		     f->new_tlb_gen <= local_tlb_gen)) {  in flush_tlb_func()
797 		 * The TLB is already up to date in respect to f->new_tlb_gen.  in flush_tlb_func()
809 	mm_tlb_gen = atomic64_read(&loaded_mm->context.tlb_gen);  in flush_tlb_func()
814 		 * happen if two concurrent flushes happen -- the first flush to  in flush_tlb_func()
822 	WARN_ON_ONCE(f->new_tlb_gen > mm_tlb_gen);  in flush_tlb_func()
825 	 * If we get to this point, we know that our TLB is out of date.  in flush_tlb_func()
827 	 * possible that f->new_tlb_gen <= local_tlb_gen), but we're  in flush_tlb_func()
836 	 * 1. f->new_tlb_gen == local_tlb_gen + 1.  We have an invariant that  in flush_tlb_func()
839 	 *    f->new_tlb_gen == 3, then we know that the flush needed to bring  in flush_tlb_func()
850 	 *    3, we'd be break the invariant: we'd update local_tlb_gen above  in flush_tlb_func()
853 	 * 2. f->new_tlb_gen == mm_tlb_gen.  This is purely an optimization.  in flush_tlb_func()
854 	 *    Partial TLB flushes are not all that much cheaper than full TLB  in flush_tlb_func()
856 	 *    to do a partial flush if that won't bring our TLB fully up to  in flush_tlb_func()
861 	if (f->end != TLB_FLUSH_ALL &&  in flush_tlb_func()
862 	    f->new_tlb_gen == local_tlb_gen + 1 &&  in flush_tlb_func()
863 	    f->new_tlb_gen == mm_tlb_gen) {  in flush_tlb_func()
865 		unsigned long addr = f->start;  in flush_tlb_func()
868 		VM_WARN_ON(f->new_tlb_gen == TLB_GENERATION_INVALID);  in flush_tlb_func()
871 		VM_WARN_ON(f->mm == NULL);  in flush_tlb_func()
873 		nr_invalidate = (f->end - f->start) >> f->stride_shift;  in flush_tlb_func()
875 		while (addr < f->end) {  in flush_tlb_func()
877 			addr += 1UL << f->stride_shift;  in flush_tlb_func()
896 				(f->mm == NULL) ? TLB_LOCAL_SHOOTDOWN :  in flush_tlb_func()
914 	 * cases in which a remote TLB flush will be traced, but eventually  in native_flush_tlb_multi()
918 	if (info->end == TLB_FLUSH_ALL)  in native_flush_tlb_multi()
922 				(info->end - info->start) >> PAGE_SHIFT);  in native_flush_tlb_multi()
926 	 * CPUs in lazy TLB mode. They will flush the CPU themselves  in native_flush_tlb_multi()
930 	 * IPI everywhere, to prevent CPUs in lazy TLB mode from tripping  in native_flush_tlb_multi()
934 	if (info->freed_tables)  in native_flush_tlb_multi()
948  * See Documentation/arch/x86/tlb.rst for details.  We choose 33
974 	 * Ensure that the following code is non-reentrant and flush_tlb_info  in get_flush_tlb_info()
975 	 * is not overwritten. This means no TLB flushing is initiated by  in get_flush_tlb_info()
976 	 * interrupt handlers and machine-check exception handlers.  in get_flush_tlb_info()
981 	info->start		= start;  in get_flush_tlb_info()
982 	info->end		= end;  in get_flush_tlb_info()
983 	info->mm		= mm;  in get_flush_tlb_info()
984 	info->stride_shift	= stride_shift;  in get_flush_tlb_info()
985 	info->freed_tables	= freed_tables;  in get_flush_tlb_info()
986 	info->new_tlb_gen	= new_tlb_gen;  in get_flush_tlb_info()
987 	info->initiating_cpu	= smp_processor_id();  in get_flush_tlb_info()
1013 	    ((end - start) >> stride_shift) > tlb_single_page_flush_ceiling) {  in flush_tlb_mm_range()
1026 	 * a local TLB flush is needed. Optimize this use-case by calling  in flush_tlb_mm_range()
1062 	for (addr = f->start; addr < f->end; addr += PAGE_SIZE)  in do_kernel_range_flush()
1070 	    (end - start) > tlb_single_page_flush_ceiling << PAGE_SHIFT) {  in flush_tlb_kernel_range()
1096 		build_cr3(this_cpu_read(cpu_tlbstate.loaded_mm)->pgd,  in __get_current_cr3_fast()
1121 	 * If PTI is on, then the kernel is mapped with non-global PTEs, and  in flush_tlb_one_kernel()
1193 	 * Read-modify-write to CR4 - protect it from preemption and  in native_flush_tlb_global()
1218 	/* If current->mm == NULL then the read_cr3() "borrows" an mm */  in native_flush_tlb_local()
1242 		 * !PGE -> !PCID (setup_pcid()), thus every flush is total.  in __flush_tlb_all()
1259 	 * a local TLB flush is needed. Optimize this use-case by calling  in arch_tlbbatch_flush()
1262 	if (cpumask_any_but(&batch->cpumask, cpu) < nr_cpu_ids) {  in arch_tlbbatch_flush()
1263 		flush_tlb_multi(&batch->cpumask, info);  in arch_tlbbatch_flush()
1264 	} else if (cpumask_test_cpu(cpu, &batch->cpumask)) {  in arch_tlbbatch_flush()
1271 	cpumask_clear(&batch->cpumask);  in arch_tlbbatch_flush()
1287 	struct mm_struct *current_mm = current->mm;  in nmi_uaccess_okay()
1293 	 * current_mm->pgd == __va(read_cr3_pa()).  This may be slow, though,  in nmi_uaccess_okay()
1299 	 * sets loaded_mm to LOADED_MM_SWITCHING before writing to CR3.  in nmi_uaccess_okay()
1304 	VM_WARN_ON_ONCE(current_mm->pgd != __va(read_cr3_pa()));  in nmi_uaccess_okay()
1326 	len = min(count, sizeof(buf) - 1);  in tlbflush_write_file()
1328 		return -EFAULT;  in tlbflush_write_file()
1332 		return -EINVAL;  in tlbflush_write_file()
1335 		return -EINVAL;  in tlbflush_write_file()