kvm/mmu/spte.c

1 // SPDX-License-Identifier: GPL-2.0-only
3  * Kernel-based Virtual Machine driver for Linux
52 	 * KVM can actually enable MMIO caching depends on vendor-specific  in kvm_mmu_spte_module_init()
73 	u64 gen = kvm_vcpu_memslots(vcpu)->generation & MMIO_SPTE_GEN_MASK;  in make_mmio_spte()
100 			 * and only treat UC/UC-/WC pages as MMIO.  in kvm_is_mmio_pfn()
105 				     pfn_to_hpa(pfn + 1) - 1,  in kvm_is_mmio_pfn()
111  * The caller is responsible for checking if the SPTE is shadow-present, and
112  * for determining whether or not the caller cares about non-leaf SPTEs.
118 	 * out of mmu-lock, it can ensure dirty bit is not lost,  in spte_has_volatile_bits()
143 	int level = sp->role.level;  in make_spte()
149 	if (sp->role.ad_disabled)  in make_spte()
156 	 * supports exec-only page table entries.  In that case,  in make_spte()
177 	    is_nx_huge_page_enabled(vcpu->kvm)) {  in make_spte()
219 		 * SPTE.  Write-protect the SPTE if the page can't be unsync'd,  in make_spte()
220 		 * e.g. it's write-tracked (upper-level SPs) or has one or more  in make_spte()
223 		if (mmu_try_to_unsync_pages(vcpu->kvm, slot, gfn, can_unsync, prefetch)) {  in make_spte()
237 	WARN_ONCE(is_rsvd_spte(&vcpu->arch.mmu->shadow_zero_check, spte, level),  in make_spte()
239 		  get_rsvd_bits(&vcpu->arch.mmu->shadow_zero_check, spte, level));  in make_spte()
244 		mark_page_dirty_in_slot(vcpu->kvm, slot, gfn);  in make_spte()
268  * Construct an SPTE that maps a sub-page of the given huge page SPTE where
269  * `index` identifies which sub-page.
446 	 * of an EPT paging-structure entry is 110b (write/execute).  in kvm_mmu_set_ept_masks()
474 			  52 - SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)) {  in kvm_mmu_reset_all_pte_masks()
476 			- SHADOW_NONPRESENT_OR_RSVD_MASK_LEN;  in kvm_mmu_reset_all_pte_masks()
478 			rsvd_bits(low_phys_bits, boot_cpu_data.x86_cache_bits - 1);  in kvm_mmu_reset_all_pte_masks()
482 		GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT);  in kvm_mmu_reset_all_pte_masks()
506 	 * PFEC.RSVD=1 on MMIO accesses.  64-bit PTEs (PAE, x86-64, and EPT  in kvm_mmu_reset_all_pte_masks()
508 	 * 52-bit physical addresses then there are no reserved PA bits in the  in kvm_mmu_reset_all_pte_masks()