Lines Matching +full:sw +full:- +full:exception

1 // SPDX-License-Identifier: GPL-2.0-only
15 * Copyright (c) 2010-17: Borislav Petkov <bp@alien8.de>
48 SW_INJ = 0, /* SW injection, simply decode the error */
56 [SW_INJ] = "sw",
71 m->reg = val; \
85 *val = m->reg; \
100 /* Use the user provided IPID value on a sw injection. */
107 m->ipid = val; in inj_ipid_set()
119 m->cpuvendor = boot_cpu_data.x86_vendor; in setup_inj_struct()
120 m->time = ktime_get_real_seconds(); in setup_inj_struct()
121 m->cpuid = cpuid_eax(1); in setup_inj_struct()
122 m->microcode = boot_cpu_data.microcode; in setup_inj_struct()
128 struct mce *i = &per_cpu(injectm, m->extcpu); in inject_mce()
131 i->finished = 0; in inject_mce()
133 m->finished = 0; in inject_mce()
135 i->extcpu = m->extcpu; in inject_mce()
141 i->finished = 1; in inject_mce()
153 m->finished = 0; in raise_poll()
163 regs.ip = m->ip; in raise_exception()
164 regs.cs = m->cs; in raise_exception()
167 /* do_machine_check() expects interrupts disabled -- at least */ in raise_exception()
171 m->finished = 0; in raise_exception()
184 if (m->inject_flags & MCJ_EXCEPTION) in mce_raise_notify()
186 else if (m->status) in mce_raise_notify()
197 m->inject_flags & MCJ_EXCEPTION) { in mce_irq_ipi()
207 int context = MCJ_CTX(m->inject_flags); in raise_local()
209 int cpu = m->extcpu; in raise_local()
211 if (m->inject_flags & MCJ_EXCEPTION) { in raise_local()
212 pr_info("Triggering MCE exception on CPU %d\n", cpu); in raise_local()
226 ret = -EINVAL; in raise_local()
228 pr_info("MCE exception done on CPU %d\n", cpu); in raise_local()
229 } else if (m->status) { in raise_local()
235 m->finished = 0; in raise_local()
242 int context = MCJ_CTX(m->inject_flags); in raise_mce()
249 if (m->inject_flags & (MCJ_IRQ_BROADCAST | MCJ_NMI_BROADCAST)) { in raise_mce()
258 if (!mcpu->finished || in raise_mce()
259 MCJ_CTX(mcpu->inject_flags) != MCJ_CTX_RANDOM) in raise_mce()
263 if (m->inject_flags & MCJ_IRQ_BROADCAST) { in raise_mce()
272 } else if (m->inject_flags & MCJ_NMI_BROADCAST) in raise_mce()
349 return -EINVAL; in __set_inj()
370 return -EINVAL; in flags_write()
373 return -EFAULT; in flags_write()
375 buf[cnt - 1] = 0; in flags_write()
408 return -EINVAL; in inj_extcpu_set()
410 m->extcpu = val; in inj_extcpu_set()
436 cores_per_node = (c->x86_max_cores * smp_num_siblings) / amd_get_nodes_per_socket(); in get_nbc_for_node()
452 F3 = nb->misc; in toggle_nb_mca_mst_cpu()
459 __func__, PCI_FUNC(F3->devfn), NBCFG); in toggle_nb_mca_mst_cpu()
473 __func__, PCI_FUNC(F3->devfn), NBCFG); in toggle_nb_mca_mst_cpu()
530 * - MCx_STATUS[Deferred]: make sure it is a deferred error in do_inject()
531 * - MCx_STATUS[UC] cleared: deferred errors are _not_ UC in do_inject()
588 /* Get bank count on target CPU so we can handle non-uniform values. */ in inj_bank_set()
589 rdmsrl_on_cpu(m->extcpu, MSR_IA32_MCG_CAP, &cap); in inj_bank_set()
593 pr_err("MCA bank %llu non-existent on CPU%d\n", val, m->extcpu); in inj_bank_set()
594 return -EINVAL; in inj_bank_set()
597 m->bank = val; in inj_bank_set()
600 * sw-only injection allows to write arbitrary values into the MCA in inj_bank_set()
613 if (rdmsrl_on_cpu(m->extcpu, MSR_AMD64_SMCA_MCx_IPID(val), &ipid)) { in inj_bank_set()
614 pr_err("Error reading IPID on CPU%d\n", m->extcpu); in inj_bank_set()
615 return -EINVAL; in inj_bank_set()
620 return -ENODEV; in inj_bank_set()
660 "\t banks in a processor varies and is family/model-specific, therefore, the\n"
661 "\t supplied value is sanity-checked. Setting the bank value also triggers the\n"
669 "\t - \"sw\": Software error injection. Decode error to a human-readable \n"
671 "\t - \"hw\": Hardware error injection. Causes the #MC exception handler to \n"
675 "\t - \"df\": Trigger APIC interrupt for Deferred error. Causes deferred \n"
678 "\t - \"th\": Trigger APIC interrupt for Threshold errors. Causes threshold \n"
681 "ipid:\t IPID (AMD-specific)\n"
716 dfs_inj = debugfs_create_dir("mce-inject", NULL); in debugfs_init()
768 return -ENOMEM; in inject_init()