1 // SPDX-License-Identifier: GPL-2.0
22 #include <asm/intel-family.h>
67  * Processors which have self-snooping capability can handle conflicting
75 	switch (c->x86_model) {  in check_memory_type_self_snoop_errata()
107 	if (c->x86 != 6)  in probe_xeon_phi_r3mwait()
109 	switch (c->x86_model) {  in probe_xeon_phi_r3mwait()
131  * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
132  * - https://kb.vmware.com/s/article/52345
133  * - Microcode revisions observed in the wild
134  * - Release note from 20180108 microcode release
176 	if (c->x86 != 6)  in bad_spectre_microcode()
180 		if (c->x86_model == spectre_bad_microcodes[i].model &&  in bad_spectre_microcode()
181 		    c->x86_stepping == spectre_bad_microcodes[i].stepping)  in bad_spectre_microcode()
182 			return (c->microcode <= spectre_bad_microcodes[i].microcode);  in bad_spectre_microcode()
193 #define TME_ACTIVATE_POLICY(x)		((x >> 4) & 0xf)	/* Bits 7:4 */
251 	nr_keyids = (1UL << keyid_bits) - 1;  in detect_tme_early()
268 	c->x86_phys_bits -= keyid_bits;  in detect_tme_early()
276 	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {  in early_init_intel()
279 			c->cpuid_level = cpuid_eax(0);  in early_init_intel()
284 	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||  in early_init_intel()
285 		(c->x86 == 0x6 && c->x86_model >= 0x0e))  in early_init_intel()
288 	if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))  in early_init_intel()
289 		c->microcode = intel_get_microcode_revision();  in early_init_intel()
315 	if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&  in early_init_intel()
316 	    c->microcode < 0x20e) {  in early_init_intel()
325 	if (c->x86 == 15 && c->x86_cache_alignment == 64)  in early_init_intel()
326 		c->x86_cache_alignment = 128;  in early_init_intel()
330 	if (c->x86 == 0xF && c->x86_model == 0x3  in early_init_intel()
331 	    && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))  in early_init_intel()
332 		c->x86_phys_bits = 36;  in early_init_intel()
335 	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate  in early_init_intel()
336 	 * with P/T states and does not stop in deep C-states.  in early_init_intel()
339 	 * cabinets - we turn it off in that case explicitly.)  in early_init_intel()
341 	if (c->x86_power & (1 << 8)) {  in early_init_intel()
347 	if (c->x86 == 6) {  in early_init_intel()
348 		switch (c->x86_model) {  in early_init_intel()
370 	if (c->x86 == 6 && c->x86_model < 15)  in early_init_intel()
377 	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {  in early_init_intel()
396 	if (c->x86 == 5 && c->x86_model == 9) {  in early_init_intel()
446 	if (!c->cpu_index)  in intel_smp_check()
452 	if (c->x86 == 5 &&  in intel_smp_check()
453 	    c->x86_stepping >= 1 && c->x86_stepping <= 4 &&  in intel_smp_check()
454 	    c->x86_model <= 3) {  in intel_smp_check()
481 	if (c->x86 == 5 && c->x86_model < 9) {  in intel_workarounds()
486 			pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");  in intel_workarounds()
496 	if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)  in intel_workarounds()
514 	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {  in intel_workarounds()
528 	if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&  in intel_workarounds()
529 	    (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))  in intel_workarounds()
537 	switch (c->x86) {  in intel_workarounds()
538 	case 4:		/* 486: untested */  in intel_workarounds()
542 	case 6:		/* PII/PIII only like movsl with 8-byte alignment */  in intel_workarounds()
545 	case 15:	/* P4 is OK down to 8-byte alignment */  in intel_workarounds()
633 	if (c->cpuid_level > 9) {  in init_intel()
653 	if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&  in init_intel()
654 	    (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))  in init_intel()
657 	if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&  in init_intel()
658 		((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT)))  in init_intel()
662 	if (c->x86 == 15)  in init_intel()
663 		c->x86_cache_alignment = c->x86_clflush_size * 2;  in init_intel()
664 	if (c->x86 == 6)  in init_intel()
672 	if (c->x86 == 6) {  in init_intel()
673 		unsigned int l2 = c->x86_cache_size;  in init_intel()
676 		switch (c->x86_model) {  in init_intel()
687 			else if (c->x86_stepping == 0 || c->x86_stepping == 5)  in init_intel()
688 				p = "Celeron-A";  in init_intel()
698 			strcpy(c->x86_model_id, p);  in init_intel()
701 	if (c->x86 == 15)  in init_intel()
703 	if (c->x86 == 6)  in init_intel()
725 	 * One has 256kb of cache, the other 512. We have no way  in intel_size_cache()
729 	if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))  in intel_size_cache()
733 	 * Intel Quark SoC X1000 contains a 4-way set associative  in intel_size_cache()
736 	if ((c->x86 == 5) && (c->x86_model == 9))  in intel_size_cache()
764 	{ 0x01, TLB_INST_4K,		32,	" TLB_INST 4 KByte pages, 4-way set associative" },
765 	{ 0x02, TLB_INST_4M,		2,	" TLB_INST 4 MByte pages, full associative" },
766 	{ 0x03, TLB_DATA_4K,		64,	" TLB_DATA 4 KByte pages, 4-way set associative" },
767 	{ 0x04, TLB_DATA_4M,		8,	" TLB_DATA 4 MByte pages, 4-way set associative" },
768 	{ 0x05, TLB_DATA_4M,		32,	" TLB_DATA 4 MByte pages, 4-way set associative" },
769 	{ 0x0b, TLB_INST_4M,		4,	" TLB_INST 4 MByte pages, 4-way set associative" },
770 	{ 0x4f, TLB_INST_4K,		32,	" TLB_INST 4 KByte pages" },
771 	{ 0x50, TLB_INST_ALL,		64,	" TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
772 	{ 0x51, TLB_INST_ALL,		128,	" TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
773 	{ 0x52, TLB_INST_ALL,		256,	" TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
774 	{ 0x55, TLB_INST_2M_4M,		7,	" TLB_INST 2-MByte or 4-MByte pages, fully associative" },
775 	{ 0x56, TLB_DATA0_4M,		16,	" TLB_DATA0 4 MByte pages, 4-way set associative" },
776 	{ 0x57, TLB_DATA0_4K,		16,	" TLB_DATA0 4 KByte pages, 4-way associative" },
777 	{ 0x59, TLB_DATA0_4K,		16,	" TLB_DATA0 4 KByte pages, fully associative" },
778 	{ 0x5a, TLB_DATA0_2M_4M,	32,	" TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
779 	{ 0x5b, TLB_DATA_4K_4M,		64,	" TLB_DATA 4 KByte and 4 MByte pages" },
780 	{ 0x5c, TLB_DATA_4K_4M,		128,	" TLB_DATA 4 KByte and 4 MByte pages" },
781 	{ 0x5d, TLB_DATA_4K_4M,		256,	" TLB_DATA 4 KByte and 4 MByte pages" },
782 	{ 0x61, TLB_INST_4K,		48,	" TLB_INST 4 KByte pages, full associative" },
783 	{ 0x63, TLB_DATA_1G,		4,	" TLB_DATA 1 GByte pages, 4-way set associative" },
784 	{ 0x6b, TLB_DATA_4K,		256,	" TLB_DATA 4 KByte pages, 8-way associative" },
785 	{ 0x6c, TLB_DATA_2M_4M,		128,	" TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
787 	{ 0x76, TLB_INST_2M_4M,		8,	" TLB_INST 2-MByte or 4-MByte pages, fully associative" },
788 	{ 0xb0, TLB_INST_4K,		128,	" TLB_INST 4 KByte pages, 4-way set associative" },
789 	{ 0xb1, TLB_INST_2M_4M,		4,	" TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
790 	{ 0xb2, TLB_INST_4K,		64,	" TLB_INST 4KByte pages, 4-way set associative" },
791 	{ 0xb3, TLB_DATA_4K,		128,	" TLB_DATA 4 KByte pages, 4-way set associative" },
792 	{ 0xb4, TLB_DATA_4K,		256,	" TLB_DATA 4 KByte pages, 4-way associative" },
793 	{ 0xb5, TLB_INST_4K,		64,	" TLB_INST 4 KByte pages, 8-way set associative" },
794 	{ 0xb6, TLB_INST_4K,		128,	" TLB_INST 4 KByte pages, 8-way set associative" },
795 	{ 0xba, TLB_DATA_4K,		64,	" TLB_DATA 4 KByte pages, 4-way associative" },
796 	{ 0xc0, TLB_DATA_4K_4M,		8,	" TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
797 	{ 0xc1, STLB_4K_2M,		1024,	" STLB 4 KByte and 2 MByte pages, 8-way associative" },
798 	{ 0xc2, TLB_DATA_2M_4M,		16,	" TLB_DATA 2 MByte/4MByte pages, 4-way associative" },
799 	{ 0xca, STLB_4K,		512,	" STLB 4 KByte pages, 4-way associative" },
893 	unsigned int regs[4];  in intel_detect_tlb()
896 	if (c->cpuid_level < 2)  in intel_detect_tlb()
921 		{ .family = 4, .model_names =
923 			  [0] = "486 DX-25/33",
924 			  [1] = "486 DX-50",
927 			  [4] = "486 SL",
929 			  [7] = "486 DX/2-WB",
930 			  [8] = "486 DX/4",
931 			  [9] = "486 DX/4-WB"
936 			  [0] = "Pentium 60/66 A-step",
938 			  [2] = "Pentium 75 - 200",
940 			  [4] = "Pentium MMX",
941 			  [7] = "Mobile Pentium 75 - 200",
948 			  [0] = "Pentium Pro A-step",
951 			  [4] = "Pentium II (Deschutes)",
962 			  [0] = "Pentium 4 (Unknown)",
963 			  [1] = "Pentium 4 (Willamette)",
964 			  [2] = "Pentium 4 (Northwood)",
965 			  [4] = "Pentium 4 (Foster)",
966 			  [5] = "Pentium 4 (Foster)",
1146  * If a CPU goes offline with pending delayed work to re-enable split lock
1149  * different CPU probably won't re-enable split lock detection. This is a
1153  * Unconditionally re-enable detection here.
1167 	if (!current->reported_split_lock)  in split_lock_warn()
1169 				    current->comm, current->pid, ip);  in split_lock_warn()
1170 	current->reported_split_lock = 1;  in split_lock_warn()
1183 		if (down_interruptible(&buslock_sem) == -EINTR)  in split_lock_warn()
1206 		     current->comm, current->pid,  in handle_guest_split_lock()
1209 	current->thread.error_code = 0;  in handle_guest_split_lock()
1210 	current->thread.trap_nr = X86_TRAP_AC;  in handle_guest_split_lock()
1242 	if ((regs->flags & X86_EFLAGS_AC) || sld_state == sld_fatal)  in handle_user_split_lock()
1244 	split_lock_warn(regs->ip);  in handle_user_split_lock()
1261 				    current->comm, current->pid, regs->ip);  in handle_bus_lock()
1270  * CPU models that are known to have the per-core split-lock detection
1325 …	pr_info("#AC: crashing the kernel on kernel split_locks and warning on user-space split_locks\n");  in sld_state_show()
1330 			pr_info("#DB: warning on user-space bus_locks\n");  in sld_state_show()
1335 …pr_info("#AC: crashing the kernel on kernel split_locks and sending SIGBUS on user-space split_loc…  in sld_state_show()
1337 			pr_info("#DB: sending SIGBUS on user-space bus_locks%s\n",  in sld_state_show()
1339 				" from non-WB" : "");  in sld_state_show()
1359  * get_this_hybrid_cpu_type() - Get the type of this hybrid CPU