Lines Matching +full:wait +full:- +full:pin +full:- +full:polarity
1 // SPDX-License-Identifier: GPL-2.0
3 * Intel IO-APIC support for multi-Pentium hosts.
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
25 * - SiS APIC rmw bug:
28 * required to rewrite the index register for a read-modify-write
74 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
75 #define for_each_pin(idx, pin) \ argument
76 for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
77 #define for_each_ioapic_pin(idx, pin) \ argument
79 for_each_pin((idx), (pin))
90 int apic, pin; member
113 * Saved state during suspend/resume, or while enabling intr-remap.
146 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1; in mp_ioapic_pin_count()
149 static inline u32 mp_pin_to_gsi(int ioapic, int pin) in mp_pin_to_gsi() argument
151 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin; in mp_pin_to_gsi()
184 * disable_ioapic_support() - disables ioapic support at runtime
190 noioapicreroute = -1; in disable_ioapic_support()
197 /* disable IO-APIC */ in parse_noapic()
210 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, in mp_save_irq()
211 m->srcbusirq, m->dstapic, m->dstirq); in mp_save_irq()
272 writel(vector, &io_apic->eoi); in io_apic_eoi()
278 writel(reg, &io_apic->index); in native_io_apic_read()
279 return readl(&io_apic->data); in native_io_apic_read()
287 writel(reg, &io_apic->index); in io_apic_write()
288 writel(value, &io_apic->data); in io_apic_write()
291 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) in __ioapic_read_entry() argument
295 entry.w1 = io_apic_read(apic, 0x10 + 2 * pin); in __ioapic_read_entry()
296 entry.w2 = io_apic_read(apic, 0x11 + 2 * pin); in __ioapic_read_entry()
301 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) in ioapic_read_entry() argument
307 entry = __ioapic_read_entry(apic, pin); in ioapic_read_entry()
319 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) in __ioapic_write_entry() argument
321 io_apic_write(apic, 0x11 + 2*pin, e.w2); in __ioapic_write_entry()
322 io_apic_write(apic, 0x10 + 2*pin, e.w1); in __ioapic_write_entry()
325 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) in ioapic_write_entry() argument
330 __ioapic_write_entry(apic, pin, e); in ioapic_write_entry()
339 static void ioapic_mask_entry(int apic, int pin) in ioapic_mask_entry() argument
345 io_apic_write(apic, 0x10 + 2*pin, e.w1); in ioapic_mask_entry()
346 io_apic_write(apic, 0x11 + 2*pin, e.w2); in ioapic_mask_entry()
351 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
352 * shared ISA-space IRQs, so we have to support them. We are super
353 * fast in the common case, and fast for shared ISA-space IRQs.
356 int node, int apic, int pin) in __add_pin_to_irq_node() argument
361 for_each_irq_pin(entry, data->irq_2_pin) in __add_pin_to_irq_node()
362 if (entry->apic == apic && entry->pin == pin) in __add_pin_to_irq_node()
368 node, apic, pin); in __add_pin_to_irq_node()
369 return -ENOMEM; in __add_pin_to_irq_node()
371 entry->apic = apic; in __add_pin_to_irq_node()
372 entry->pin = pin; in __add_pin_to_irq_node()
373 list_add_tail(&entry->list, &data->irq_2_pin); in __add_pin_to_irq_node()
378 static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin) in __remove_pin_from_irq() argument
382 list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list) in __remove_pin_from_irq()
383 if (entry->apic == apic && entry->pin == pin) { in __remove_pin_from_irq()
384 list_del(&entry->list); in __remove_pin_from_irq()
391 int node, int apic, int pin) in add_pin_to_irq_node() argument
393 if (__add_pin_to_irq_node(data, node, apic, pin)) in add_pin_to_irq_node()
394 panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); in add_pin_to_irq_node()
398 * Reroute an IRQ to a different pin.
406 for_each_irq_pin(entry, data->irq_2_pin) { in replace_pin_at_irq_node()
407 if (entry->apic == oldapic && entry->pin == oldpin) { in replace_pin_at_irq_node()
408 entry->apic = newapic; in replace_pin_at_irq_node()
409 entry->pin = newpin; in replace_pin_at_irq_node()
415 /* old apic/pin didn't exist, so just add new ones */ in replace_pin_at_irq_node()
424 data->entry.masked = masked; in io_apic_modify_irq()
426 for_each_irq_pin(entry, data->irq_2_pin) { in io_apic_modify_irq()
427 io_apic_write(entry->apic, 0x10 + 2 * entry->pin, data->entry.w1); in io_apic_modify_irq()
436 * Synchronize the IO-APIC and the CPU by doing in io_apic_sync()
437 * a dummy read from the IO-APIC in io_apic_sync()
441 io_apic = io_apic_base(entry->apic); in io_apic_sync()
442 readl(&io_apic->data); in io_apic_sync()
447 struct mp_chip_data *data = irq_data->chip_data; in mask_ioapic_irq()
462 struct mp_chip_data *data = irq_data->chip_data; in unmask_ioapic_irq()
471 * IO-APIC versions below 0x20 don't support EOI register.
476 * 30h-FFh Reserved
478 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
480 * use io-apic's of version 0x20.
482 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
486 static void __eoi_ioapic_pin(int apic, int pin, int vector) in __eoi_ioapic_pin() argument
493 entry = entry1 = __ioapic_read_entry(apic, pin); in __eoi_ioapic_pin()
501 __ioapic_write_entry(apic, pin, entry1); in __eoi_ioapic_pin()
506 __ioapic_write_entry(apic, pin, entry); in __eoi_ioapic_pin()
516 for_each_irq_pin(entry, data->irq_2_pin) in eoi_ioapic_pin()
517 __eoi_ioapic_pin(entry->apic, entry->pin, vector); in eoi_ioapic_pin()
521 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) in clear_IO_APIC_pin() argument
525 /* Check delivery_mode to be sure we're not clearing an SMI pin */ in clear_IO_APIC_pin()
526 entry = ioapic_read_entry(apic, pin); in clear_IO_APIC_pin()
531 * Make sure the entry is masked and re-read the contents to check in clear_IO_APIC_pin()
532 * if it is a level triggered pin and if the remote-IRR is set. in clear_IO_APIC_pin()
536 ioapic_write_entry(apic, pin, entry); in clear_IO_APIC_pin()
537 entry = ioapic_read_entry(apic, pin); in clear_IO_APIC_pin()
545 * doesn't clear the remote-IRR if the trigger mode is not in clear_IO_APIC_pin()
550 ioapic_write_entry(apic, pin, entry); in clear_IO_APIC_pin()
553 __eoi_ioapic_pin(apic, pin, entry.vector); in clear_IO_APIC_pin()
558 * Clear the rest of the bits in the IO-APIC RTE except for the mask in clear_IO_APIC_pin()
561 ioapic_mask_entry(apic, pin); in clear_IO_APIC_pin()
562 entry = ioapic_read_entry(apic, pin); in clear_IO_APIC_pin()
564 pr_err("Unable to reset IRR for apic: %d, pin :%d\n", in clear_IO_APIC_pin()
565 mpc_ioapic_id(apic), pin); in clear_IO_APIC_pin()
570 int apic, pin; in clear_IO_APIC() local
572 for_each_ioapic_pin(apic, pin) in clear_IO_APIC()
573 clear_IO_APIC_pin(apic, pin); in clear_IO_APIC()
578 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
579 * specific CPU-side IRQs.
584 [0 ... MAX_PIRQS - 1] = -1
595 "PIRQ redirection, working around broken MP-BIOS.\n"); in ioapic_pirq_setup()
602 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); in ioapic_pirq_setup()
606 pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; in ioapic_pirq_setup()
615 * Saves all the IO-APIC RTE's
619 int apic, pin; in save_ioapic_entries() local
624 err = -ENOMEM; in save_ioapic_entries()
628 for_each_pin(apic, pin) in save_ioapic_entries()
629 ioapics[apic].saved_registers[pin] = in save_ioapic_entries()
630 ioapic_read_entry(apic, pin); in save_ioapic_entries()
641 int apic, pin; in mask_ioapic_entries() local
647 for_each_pin(apic, pin) { in mask_ioapic_entries()
650 entry = ioapics[apic].saved_registers[pin]; in mask_ioapic_entries()
653 ioapic_write_entry(apic, pin, entry); in mask_ioapic_entries()
664 int apic, pin; in restore_ioapic_entries() local
670 for_each_pin(apic, pin) in restore_ioapic_entries()
671 ioapic_write_entry(apic, pin, in restore_ioapic_entries()
672 ioapics[apic].saved_registers[pin]); in restore_ioapic_entries()
678 * Find the IRQ entry number of a certain pin.
680 static int find_irq_entry(int ioapic_idx, int pin, int type) in find_irq_entry() argument
688 mp_irqs[i].dstirq == pin) in find_irq_entry()
691 return -1; in find_irq_entry()
695 * Find the pin to which IRQ[irq] (ISA) is connected
710 return -1; in find_isa_irq_pin()
734 return -1; in find_isa_irq_apic()
742 * Determine IRQ line polarity (high active or low active): in irq_active_low()
747 * Conforms to spec, ie. bus-type dependent polarity. PCI in irq_active_low()
754 pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n"); in irq_active_low()
813 * Conforms to spec, ie. bus-type dependent trigger in irq_is_level()
830 static int __acpi_get_override_irq(u32 gsi, bool *trigger, bool *polarity) in __acpi_get_override_irq() argument
832 int ioapic, pin, idx; in __acpi_get_override_irq() local
835 return -1; in __acpi_get_override_irq()
839 return -1; in __acpi_get_override_irq()
841 pin = mp_find_ioapic_pin(ioapic, gsi); in __acpi_get_override_irq()
842 if (pin < 0) in __acpi_get_override_irq()
843 return -1; in __acpi_get_override_irq()
845 idx = find_irq_entry(ioapic, pin, mp_INT); in __acpi_get_override_irq()
847 return -1; in __acpi_get_override_irq()
850 *polarity = irq_active_low(idx); in __acpi_get_override_irq()
864 int trigger, int polarity) in ioapic_set_alloc_attr() argument
867 info->type = X86_IRQ_ALLOC_TYPE_IOAPIC; in ioapic_set_alloc_attr()
868 info->ioapic.node = node; in ioapic_set_alloc_attr()
869 info->ioapic.is_level = trigger; in ioapic_set_alloc_attr()
870 info->ioapic.active_low = polarity; in ioapic_set_alloc_attr()
871 info->ioapic.valid = 1; in ioapic_set_alloc_attr()
876 u32 gsi, int ioapic_idx, int pin) in ioapic_copy_alloc_attr() argument
881 dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC; in ioapic_copy_alloc_attr()
882 dst->devid = mpc_ioapic_id(ioapic_idx); in ioapic_copy_alloc_attr()
883 dst->ioapic.pin = pin; in ioapic_copy_alloc_attr()
884 dst->ioapic.valid = 1; in ioapic_copy_alloc_attr()
885 if (src && src->ioapic.valid) { in ioapic_copy_alloc_attr()
886 dst->ioapic.node = src->ioapic.node; in ioapic_copy_alloc_attr()
887 dst->ioapic.is_level = src->ioapic.is_level; in ioapic_copy_alloc_attr()
888 dst->ioapic.active_low = src->ioapic.active_low; in ioapic_copy_alloc_attr()
890 dst->ioapic.node = NUMA_NO_NODE; in ioapic_copy_alloc_attr()
892 dst->ioapic.is_level = level; in ioapic_copy_alloc_attr()
893 dst->ioapic.active_low = pol_low; in ioapic_copy_alloc_attr()
899 dst->ioapic.is_level = true; in ioapic_copy_alloc_attr()
900 dst->ioapic.active_low = true; in ioapic_copy_alloc_attr()
907 return (info && info->ioapic.valid) ? info->ioapic.node : NUMA_NO_NODE; in ioapic_alloc_attr_node()
933 * and polarity attributes. So allow the first user to reprogram the in mp_check_pin_attr()
934 * pin with real trigger and polarity attributes. in mp_check_pin_attr()
936 if (irq < nr_legacy_irqs() && data->count == 1) { in mp_check_pin_attr()
937 if (info->ioapic.is_level != data->is_level) in mp_check_pin_attr()
938 mp_register_handler(irq, info->ioapic.is_level); in mp_check_pin_attr()
939 data->entry.is_level = data->is_level = info->ioapic.is_level; in mp_check_pin_attr()
940 data->entry.active_low = data->active_low = info->ioapic.active_low; in mp_check_pin_attr()
943 return data->is_level == info->ioapic.is_level && in mp_check_pin_attr()
944 data->active_low == info->ioapic.active_low; in mp_check_pin_attr()
951 int irq = -1; in alloc_irq_from_domain()
957 * Dynamically allocate IRQ number for non-ISA IRQs in the first in alloc_irq_from_domain()
971 return -1; in alloc_irq_from_domain()
982 * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
983 * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
984 * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
990 int irq, int ioapic, int pin, in alloc_isa_irq_from_domain() argument
998 * Legacy ISA IRQ has already been allocated, just add pin to in alloc_isa_irq_from_domain()
999 * the pin list associated with this IRQ and program the IOAPIC in alloc_isa_irq_from_domain()
1002 if (irq_data && irq_data->parent_data) { in alloc_isa_irq_from_domain()
1004 return -EBUSY; in alloc_isa_irq_from_domain()
1005 if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic, in alloc_isa_irq_from_domain()
1006 info->ioapic.pin)) in alloc_isa_irq_from_domain()
1007 return -ENOMEM; in alloc_isa_irq_from_domain()
1009 info->flags |= X86_IRQ_ALLOC_LEGACY; in alloc_isa_irq_from_domain()
1014 data = irq_data->chip_data; in alloc_isa_irq_from_domain()
1015 data->isa_irq = true; in alloc_isa_irq_from_domain()
1022 static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin, in mp_map_pin_to_irq() argument
1032 return -ENOSYS; in mp_map_pin_to_irq()
1046 return -EINVAL; in mp_map_pin_to_irq()
1052 irq = irq_find_mapping(domain, pin); in mp_map_pin_to_irq()
1054 irq = -ENOENT; in mp_map_pin_to_irq()
1057 ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin); in mp_map_pin_to_irq()
1060 ioapic, pin, &tmp); in mp_map_pin_to_irq()
1061 else if ((irq = irq_find_mapping(domain, pin)) == 0) in mp_map_pin_to_irq()
1064 irq = -EBUSY; in mp_map_pin_to_irq()
1067 data->count++; in mp_map_pin_to_irq()
1075 static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags) in pin_2_irq() argument
1077 u32 gsi = mp_pin_to_gsi(ioapic, pin); in pin_2_irq()
1082 if (mp_irqs[idx].dstirq != pin) in pin_2_irq()
1089 if ((pin >= 16) && (pin <= 23)) { in pin_2_irq()
1090 if (pirq_entries[pin-16] != -1) { in pin_2_irq()
1091 if (!pirq_entries[pin-16]) { in pin_2_irq()
1093 "disabling PIRQ%d\n", pin-16); in pin_2_irq()
1095 int irq = pirq_entries[pin-16]; in pin_2_irq()
1097 "using PIRQ%d -> IRQ %d\n", in pin_2_irq()
1098 pin-16, irq); in pin_2_irq()
1105 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL); in pin_2_irq()
1110 int ioapic, pin, idx; in mp_map_gsi_to_irq() local
1114 return -ENODEV; in mp_map_gsi_to_irq()
1116 pin = mp_find_ioapic_pin(ioapic, gsi); in mp_map_gsi_to_irq()
1117 idx = find_irq_entry(ioapic, pin, mp_INT); in mp_map_gsi_to_irq()
1119 return -ENODEV; in mp_map_gsi_to_irq()
1121 return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info); in mp_map_gsi_to_irq()
1129 if (!irq_data || !irq_data->domain) in mp_unmap_irq()
1132 data = irq_data->chip_data; in mp_unmap_irq()
1133 if (!data || data->isa_irq) in mp_unmap_irq()
1137 if (--data->count == 0) in mp_unmap_irq()
1146 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) in IO_APIC_get_PCI_irq_vector() argument
1148 int irq, i, best_ioapic = -1, best_idx = -1; in IO_APIC_get_PCI_irq_vector()
1151 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", in IO_APIC_get_PCI_irq_vector()
1152 bus, slot, pin); in IO_APIC_get_PCI_irq_vector()
1156 return -1; in IO_APIC_get_PCI_irq_vector()
1181 if (pin == (mp_irqs[i].srcbusirq & 3)) { in IO_APIC_get_PCI_irq_vector()
1188 * Use the first all-but-pin matching entry as a in IO_APIC_get_PCI_irq_vector()
1189 * best-guess fuzzy result for broken mptables. in IO_APIC_get_PCI_irq_vector()
1197 return -1; in IO_APIC_get_PCI_irq_vector()
1209 unsigned int ioapic, pin; in setup_IO_APIC_irqs() local
1214 for_each_ioapic_pin(ioapic, pin) { in setup_IO_APIC_irqs()
1215 idx = find_irq_entry(ioapic, pin, mp_INT); in setup_IO_APIC_irqs()
1218 KERN_DEBUG " apic %d pin %d not connected\n", in setup_IO_APIC_irqs()
1219 mpc_ioapic_id(ioapic), pin); in setup_IO_APIC_irqs()
1221 pin_2_irq(idx, ioapic, pin, in setup_IO_APIC_irqs()
1241 " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)", in io_apic_print_entries()
1324 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", in print_IO_APICs()
1337 printk(KERN_DEBUG "IRQ to pin mappings:\n"); in print_IO_APICs()
1349 if (list_empty(&data->irq_2_pin)) in print_IO_APICs()
1353 for_each_irq_pin(entry, data->irq_2_pin) in print_IO_APICs()
1354 pr_cont("-> %d:%d", entry->apic, entry->pin); in print_IO_APICs()
1362 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; member
1367 int apic, pin; in enable_IO_APIC() local
1375 for_each_ioapic_pin(apic, pin) { in enable_IO_APIC()
1377 struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin); in enable_IO_APIC()
1380 * I have found the pin where the i8259 is connected. in enable_IO_APIC()
1385 ioapic_i8259.pin = pin; in enable_IO_APIC()
1391 /* If we could not find the appropriate pin by looking at the ioapic in enable_IO_APIC()
1398 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { in enable_IO_APIC()
1400 ioapic_i8259.pin = i8259_pin; in enable_IO_APIC()
1404 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && in enable_IO_APIC()
1405 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) in enable_IO_APIC()
1411 * Do not trust the IO-APIC being empty at bootup in enable_IO_APIC()
1423 if (ioapic_i8259.pin != -1) { in native_restore_boot_irq_mode()
1437 * Add it to the IO-APIC irq-routing table: in native_restore_boot_irq_mode()
1439 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); in native_restore_boot_irq_mode()
1443 disconnect_bsp_APIC(ioapic_i8259.pin != -1); in native_restore_boot_irq_mode()
1456 * function to set the IO-APIC physical IDs based on the
1474 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); in setup_ioapic_ids_from_mpc_nocheck()
1488 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", in setup_ioapic_ids_from_mpc_nocheck()
1498 * 'stuck on smp_invalidate_needed IPI wait' messages. in setup_ioapic_ids_from_mpc_nocheck()
1500 if (apic->check_apicid_used(&phys_id_present_map, in setup_ioapic_ids_from_mpc_nocheck()
1502 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", in setup_ioapic_ids_from_mpc_nocheck()
1537 "...changing IO-APIC physical APIC ID to %d ...", in setup_ioapic_ids_from_mpc_nocheck()
1599 } while ((now - start) < 40000000000ULL / HZ && in delay_with_tsc()
1624 * - timer IRQ defaults to IO-APIC IRQ
1625 * - if this function detects that timer IRQs are defunct, then we fall
1644 * ticks in a non-ExtINT mode. Also the local APIC in timer_irq_works()
1669 * Starting up a edge-triggered IO-APIC interrupt is
1670 * nasty - we need to make sure that we get the edge.
1674 * This is not complete - we should be able to fake
1679 int was_pending = 0, irq = data->irq; in startup_ioapic_irq()
1684 legacy_pic->mask(irq); in startup_ioapic_irq()
1685 if (legacy_pic->irq_pending(irq)) in startup_ioapic_irq()
1688 __unmask_ioapic(data->chip_data); in startup_ioapic_irq()
1703 for_each_irq_pin(entry, data->irq_2_pin) { in io_apic_level_ack_pending()
1705 int pin; in io_apic_level_ack_pending() local
1707 pin = entry->pin; in io_apic_level_ack_pending()
1708 e.w1 = io_apic_read(entry->apic, 0x10 + pin*2); in io_apic_level_ack_pending()
1743 * - On any sane system the read of the ioapic will in ioapic_finish_move()
1746 * - We get to see if the ACK has actually been delivered. in ioapic_finish_move()
1760 if (!io_apic_level_ack_pending(data->chip_data)) in ioapic_finish_move()
1790 * chipsets). Under certain conditions a level-triggered interrupt is in ioapic_ack_level()
1791 * erroneously delivered as edge-triggered one but the respective IRR in ioapic_ack_level()
1802 * level-triggered interrupt. We mask the source for the time of the in ioapic_ack_level()
1803 * operation to prevent an edge-triggered interrupt escaping meanwhile. in ioapic_ack_level()
1804 * The idea is from Manfred Spraul. --macro in ioapic_ack_level()
1810 * level-triggered io-apic interrupt will be seen as an edge in ioapic_ack_level()
1812 * to be broadcasted to the IO-APIC's which will clear the remoteIRR in ioapic_ack_level()
1813 * corresponding to the level-triggered interrupt. Hence on IO-APIC's in ioapic_ack_level()
1815 * remote IRR and on IO-APIC's which don't have an EOI register, in ioapic_ack_level()
1819 i = cfg->vector; in ioapic_ack_level()
1830 * message via io-apic EOI register write or simulating it using in ioapic_ack_level()
1837 eoi_ioapic_pin(cfg->vector, irq_data->chip_data); in ioapic_ack_level()
1845 struct mp_chip_data *data = irq_data->chip_data; in ioapic_ir_ack_level()
1848 * Intr-remapping uses pin number as the virtual vector in ioapic_ir_ack_level()
1850 * intr-remapping table entry. Hence for the io-apic in ioapic_ir_ack_level()
1851 * EOI we use the pin number. in ioapic_ir_ack_level()
1854 eoi_ioapic_pin(data->entry.vector, data); in ioapic_ir_ack_level()
1882 * - Real vector in ioapic_setup_msg_from_msi()
1883 * - DMAR/IR: 8bit subhandle (ioapic.pin) in ioapic_setup_msg_from_msi()
1884 * - AMD/IR: 8bit IRTE index in ioapic_setup_msg_from_msi()
1886 entry->vector = msg.arch_data.vector; in ioapic_setup_msg_from_msi()
1888 entry->delivery_mode = msg.arch_data.delivery_mode; in ioapic_setup_msg_from_msi()
1890 entry->dest_mode_logical = msg.arch_addr_lo.dest_mode_logical; in ioapic_setup_msg_from_msi()
1892 entry->ir_format = msg.arch_addr_lo.dmar_format; in ioapic_setup_msg_from_msi()
1894 * - DMAR/IR: index bit 0-14. in ioapic_setup_msg_from_msi()
1896 * - Virt: If the host supports x2apic without a virtualized IR in ioapic_setup_msg_from_msi()
1897 * unit then bit 0-6 of dmar_index_0_14 are providing bit in ioapic_setup_msg_from_msi()
1898 * 8-14 of the destination id. in ioapic_setup_msg_from_msi()
1900 * All other modes have bit 0-6 of dmar_index_0_14 cleared and the in ioapic_setup_msg_from_msi()
1901 * topmost 8 bits are destination id bit 0-7 (entry::destid_0_7). in ioapic_setup_msg_from_msi()
1903 entry->ir_index_0_14 = msg.arch_addr_lo.dmar_index_0_14; in ioapic_setup_msg_from_msi()
1908 struct mp_chip_data *mpd = irqd->chip_data; in ioapic_configure_entry()
1911 ioapic_setup_msg_from_msi(irqd, &mpd->entry); in ioapic_configure_entry()
1913 for_each_irq_pin(entry, mpd->irq_2_pin) in ioapic_configure_entry()
1914 __ioapic_write_entry(entry->apic, entry->pin, mpd->entry); in ioapic_configure_entry()
1920 struct irq_data *parent = irq_data->parent_data; in ioapic_set_affinity()
1924 ret = parent->chip->irq_set_affinity(parent, mask, force); in ioapic_set_affinity()
1934 * Interrupt shutdown masks the ioapic pin, but the interrupt might already
1945 * Verify that the corresponding Remote-IRR bits are clear.
1951 struct mp_chip_data *mcd = irqd->chip_data; in ioapic_irq_get_chip_state()
1956 return -EINVAL; in ioapic_irq_get_chip_state()
1960 for_each_irq_pin(p, mcd->irq_2_pin) { in ioapic_irq_get_chip_state()
1961 rentry = __ioapic_read_entry(p->apic, p->pin); in ioapic_irq_get_chip_state()
1965 * irrelevant because the IO-APIC treats them as fire and in ioapic_irq_get_chip_state()
1978 .name = "IO-APIC",
1992 .name = "IR-IO-APIC",
2012 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { in init_IO_APIC_traps()
2015 * so default to an old-fashioned 8259 in init_IO_APIC_traps()
2019 legacy_pic->make_irq(irq); in init_IO_APIC_traps()
2028 * The local APIC irq-chip implementation:
2053 .name = "local-APIC",
2070 * cycles as some i82489DX-based boards have glue logic that keeps the
2071 * 8259A interrupt line asserted until INTA. --macro
2075 int apic, pin, i; in unlock_ExtINT_logic() local
2080 pin = find_isa_irq_pin(8, mp_INT); in unlock_ExtINT_logic()
2081 if (pin == -1) { in unlock_ExtINT_logic()
2086 if (apic == -1) { in unlock_ExtINT_logic()
2091 entry0 = ioapic_read_entry(apic, pin); in unlock_ExtINT_logic()
2092 clear_IO_APIC_pin(apic, pin); in unlock_ExtINT_logic()
2106 ioapic_write_entry(apic, pin, entry1); in unlock_ExtINT_logic()
2115 while (i-- > 0) { in unlock_ExtINT_logic()
2118 i -= 10; in unlock_ExtINT_logic()
2123 clear_IO_APIC_pin(apic, pin); in unlock_ExtINT_logic()
2125 ioapic_write_entry(apic, pin, entry0); in unlock_ExtINT_logic()
2129 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2137 static int mp_alloc_timer_irq(int ioapic, int pin) in mp_alloc_timer_irq() argument
2139 int irq = -1; in mp_alloc_timer_irq()
2147 info.ioapic.pin = pin; in mp_alloc_timer_irq()
2149 irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info); in mp_alloc_timer_irq()
2167 struct mp_chip_data *data = irq_data->chip_data; in check_timer()
2181 legacy_pic->mask(0); in check_timer()
2188 * watchdog as that APIC treats NMIs as level-triggered. in check_timer()
2193 legacy_pic->init(1); in check_timer()
2197 pin2 = ioapic_i8259.pin; in check_timer()
2202 cfg->vector, apic1, pin1, apic2, pin2); in check_timer()
2207 * interrupt input. So just in case, if only one pin in check_timer()
2211 if (pin1 == -1) { in check_timer()
2212 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC"); in check_timer()
2216 } else if (pin2 == -1) { in check_timer()
2221 if (pin1 != -1) { in check_timer()
2228 * so only need to unmask if it is level-trigger in check_timer()
2233 if (idx != -1 && irq_is_level(idx)) in check_timer()
2243 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC"); in check_timer()
2246 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " in check_timer()
2247 "8254 timer not connected to IO-APIC\n"); in check_timer()
2252 "..... (found apic %d pin %d) ...\n", apic2, pin2); in check_timer()
2259 legacy_pic->unmask(0); in check_timer()
2267 legacy_pic->mask(0); in check_timer()
2276 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ in check_timer()
2277 legacy_pic->unmask(0); in check_timer()
2283 legacy_pic->mask(0); in check_timer()
2284 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); in check_timer()
2290 legacy_pic->init(0); in check_timer()
2291 legacy_pic->make_irq(0); in check_timer()
2293 legacy_pic->unmask(0); in check_timer()
2304 "Perhaps problem with the pre-enabled x2apic mode\n" in check_timer()
2305 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n"); in check_timer()
2306 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " in check_timer()
2314 * to devices. However there may be an I/O APIC pin available for
2315 * this interrupt regardless. The pin may be left unconnected, but
2317 * the master 8259A. In the MPS case such a pin will normally be
2321 * interrupt, that is edge-triggered and unmasked by default. We
2327 * it anyway. --macro
2336 struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg; in mp_irqdomain_create()
2341 if (cfg->type == IOAPIC_DOMAIN_INVALID) in mp_irqdomain_create()
2345 if (cfg->dev) { in mp_irqdomain_create()
2346 fn = of_node_to_fwnode(cfg->dev); in mp_irqdomain_create()
2348 fn = irq_domain_alloc_named_id_fwnode("IO-APIC", mpc_ioapic_id(ioapic)); in mp_irqdomain_create()
2350 return -ENOMEM; in mp_irqdomain_create()
2359 if (!cfg->dev) in mp_irqdomain_create()
2361 return -ENODEV; in mp_irqdomain_create()
2364 ip->irqdomain = irq_domain_create_hierarchy(parent, 0, hwirqs, fn, cfg->ops, in mp_irqdomain_create()
2366 if (!ip->irqdomain) { in mp_irqdomain_create()
2368 if (!cfg->dev) in mp_irqdomain_create()
2370 return -ENOMEM; in mp_irqdomain_create()
2373 if (cfg->type == IOAPIC_DOMAIN_LEGACY || in mp_irqdomain_create()
2374 cfg->type == IOAPIC_DOMAIN_STRICT) in mp_irqdomain_create()
2376 gsi_cfg->gsi_end + 1); in mp_irqdomain_create()
2384 struct fwnode_handle *fn = ioapics[idx].irqdomain->fwnode; in ioapic_destroy_irqdomain()
2388 if (!cfg->dev) in ioapic_destroy_irqdomain()
2403 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); in setup_IO_APIC()
2408 * Set up IO-APIC IRQ routing. in setup_IO_APIC()
2508 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full in io_apic_get_unique_id()
2513 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); in io_apic_get_unique_id()
2527 * 'stuck on smp_invalidate_needed IPI wait' messages. in io_apic_get_unique_id()
2529 if (apic->check_apicid_used(&apic_id_map, apic_id)) { in io_apic_get_unique_id()
2532 if (!apic->check_apicid_used(&apic_id_map, i)) in io_apic_get_unique_id()
2560 return -1; in io_apic_get_unique_id()
2684 * Ensure fixmaps for IO-APIC MMIO respect memory encryption pgprot in io_apic_set_fixmap()
2710 "WARNING: bogus zero IO-APIC " in io_apic_init_mappings()
2735 ioapic_res->start = ioapic_phys; in io_apic_init_mappings()
2736 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; in io_apic_init_mappings()
2764 return -1; in mp_find_ioapic()
2769 if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end) in mp_find_ioapic()
2774 return -1; in mp_find_ioapic()
2782 return -1; in mp_find_ioapic_pin()
2785 if (WARN_ON(gsi > gsi_cfg->gsi_end)) in mp_find_ioapic_pin()
2786 return -1; in mp_find_ioapic_pin()
2788 return gsi - gsi_cfg->gsi_base; in mp_find_ioapic_pin()
2801 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) { in bad_ioapic_register()
2822 * mp_register_ioapic - Register an IOAPIC device
2838 return -EINVAL; in mp_register_ioapic()
2844 return -EEXIST; in mp_register_ioapic()
2851 return -ENOSPC; in mp_register_ioapic()
2861 return -ENODEV; in mp_register_ioapic()
2868 * Build basic GSI lookup table to facilitate gsi->io_apic lookups in mp_register_ioapic()
2872 gsi_end = gsi_base + entries - 1; in mp_register_ioapic()
2875 if ((gsi_base >= gsi_cfg->gsi_base && in mp_register_ioapic()
2876 gsi_base <= gsi_cfg->gsi_end) || in mp_register_ioapic()
2877 (gsi_end >= gsi_cfg->gsi_base && in mp_register_ioapic()
2878 gsi_end <= gsi_cfg->gsi_end)) { in mp_register_ioapic()
2879 pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n", in mp_register_ioapic()
2881 gsi_cfg->gsi_base, gsi_cfg->gsi_end); in mp_register_ioapic()
2883 return -ENOSPC; in mp_register_ioapic()
2887 gsi_cfg->gsi_base = gsi_base; in mp_register_ioapic()
2888 gsi_cfg->gsi_end = gsi_end; in mp_register_ioapic()
2901 return -ENOMEM; in mp_register_ioapic()
2906 if (gsi_cfg->gsi_end >= gsi_top) in mp_register_ioapic()
2907 gsi_top = gsi_cfg->gsi_end + 1; in mp_register_ioapic()
2914 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n", in mp_register_ioapic()
2917 gsi_cfg->gsi_base, gsi_cfg->gsi_end); in mp_register_ioapic()
2924 int ioapic, pin; in mp_unregister_ioapic() local
2934 return -ENODEV; in mp_unregister_ioapic()
2937 for_each_pin(ioapic, pin) { in mp_unregister_ioapic()
2938 u32 gsi = mp_pin_to_gsi(ioapic, pin); in mp_unregister_ioapic()
2944 if (data && data->count) { in mp_unregister_ioapic()
2945 pr_warn("pin%d on IOAPIC%d is still in use.\n", in mp_unregister_ioapic()
2946 pin, ioapic); in mp_unregister_ioapic()
2947 return -EBUSY; in mp_unregister_ioapic()
2978 if (info && info->ioapic.valid) { in mp_irqdomain_get_attr()
2979 data->is_level = info->ioapic.is_level; in mp_irqdomain_get_attr()
2980 data->active_low = info->ioapic.active_low; in mp_irqdomain_get_attr()
2981 } else if (__acpi_get_override_irq(gsi, &data->is_level, in mp_irqdomain_get_attr()
2982 &data->active_low) < 0) { in mp_irqdomain_get_attr()
2984 data->is_level = true; in mp_irqdomain_get_attr()
2985 data->active_low = true; in mp_irqdomain_get_attr()
2990 * Configure the I/O-APIC specific fields in the routing entry.
2992 * This is important to setup the I/O-APIC specific bits (is_level,
2994 * provide the routing information and is oblivious of the I/O-APIC
3003 struct IO_APIC_route_entry *entry = &data->entry; in mp_preconfigure_entry()
3006 entry->is_level = data->is_level; in mp_preconfigure_entry()
3007 entry->active_low = data->active_low; in mp_preconfigure_entry()
3012 entry->masked = data->is_level; in mp_preconfigure_entry()
3021 int ret, ioapic, pin; in mp_irqdomain_alloc() local
3025 return -EINVAL; in mp_irqdomain_alloc()
3028 return -EINVAL; in mp_irqdomain_alloc()
3031 pin = info->ioapic.pin; in mp_irqdomain_alloc()
3032 if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0) in mp_irqdomain_alloc()
3033 return -EEXIST; in mp_irqdomain_alloc()
3037 return -ENOMEM; in mp_irqdomain_alloc()
3045 INIT_LIST_HEAD(&data->irq_2_pin); in mp_irqdomain_alloc()
3046 irq_data->hwirq = info->ioapic.pin; in mp_irqdomain_alloc()
3047 irq_data->chip = (domain->parent == x86_vector_domain) ? in mp_irqdomain_alloc()
3049 irq_data->chip_data = data; in mp_irqdomain_alloc()
3050 mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info); in mp_irqdomain_alloc()
3052 add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin); in mp_irqdomain_alloc()
3055 mp_register_handler(virq, data->is_level); in mp_irqdomain_alloc()
3059 legacy_pic->mask(virq); in mp_irqdomain_alloc()
3063 "IOAPIC[%d]: Preconfigured routing entry (%d-%d -> IRQ %d Level:%i ActiveLow:%i)\n", in mp_irqdomain_alloc()
3064 ioapic, mpc_ioapic_id(ioapic), pin, virq, in mp_irqdomain_alloc()
3065 data->is_level, data->active_low); in mp_irqdomain_alloc()
3077 if (irq_data && irq_data->chip_data) { in mp_irqdomain_free()
3078 data = irq_data->chip_data; in mp_irqdomain_free()
3080 (int)irq_data->hwirq); in mp_irqdomain_free()
3081 WARN_ON(!list_empty(&data->irq_2_pin)); in mp_irqdomain_free()
3082 kfree(irq_data->chip_data); in mp_irqdomain_free()
3103 (int)irq_data->hwirq); in mp_irqdomain_deactivate()
3108 return (int)(long)domain->host_data; in mp_irqdomain_ioapic_idx()