Lines Matching +full:0 +full:x00000802
22 #define VMCS_CONTROL_BIT(x) BIT(VMX_FEATURE_##x & 0x1f)
50 #define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x0401e172
93 #define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016
95 #define VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
96 #define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
97 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
98 #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
99 #define VM_EXIT_SAVE_IA32_PAT 0x00040000
100 #define VM_EXIT_LOAD_IA32_PAT 0x00080000
101 #define VM_EXIT_SAVE_IA32_EFER 0x00100000
102 #define VM_EXIT_LOAD_IA32_EFER 0x00200000
103 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
104 #define VM_EXIT_CLEAR_BNDCFGS 0x00800000
105 #define VM_EXIT_PT_CONCEAL_PIP 0x01000000
106 #define VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000
108 #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR 0x00036dff
110 #define VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
111 #define VM_ENTRY_IA32E_MODE 0x00000200
112 #define VM_ENTRY_SMM 0x00000400
113 #define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
114 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
115 #define VM_ENTRY_LOAD_IA32_PAT 0x00004000
116 #define VM_ENTRY_LOAD_IA32_EFER 0x00008000
117 #define VM_ENTRY_LOAD_BNDCFGS 0x00010000
118 #define VM_ENTRY_PT_CONCEAL_PIP 0x00020000
119 #define VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
121 #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR 0x000011ff
123 #define VMX_MISC_PREEMPTION_TIMER_RATE_MASK 0x0000001f
124 #define VMX_MISC_SAVE_EFER_LMA 0x00000020
125 #define VMX_MISC_ACTIVITY_HLT 0x00000040
126 #define VMX_MISC_ACTIVITY_WAIT_SIPI 0x00000100
127 #define VMX_MISC_ZERO_LEN_INS 0x40000000
131 #define VMFUNC_CONTROL_BIT(x) BIT((VMX_FEATURE_##x & 0x1f) - 28)
138 return vmx_basic & GENMASK_ULL(30, 0); in vmx_basic_vmcs_revision_id()
168 VIRTUAL_PROCESSOR_ID = 0x00000000,
169 POSTED_INTR_NV = 0x00000002,
170 LAST_PID_POINTER_INDEX = 0x00000008,
171 GUEST_ES_SELECTOR = 0x00000800,
172 GUEST_CS_SELECTOR = 0x00000802,
173 GUEST_SS_SELECTOR = 0x00000804,
174 GUEST_DS_SELECTOR = 0x00000806,
175 GUEST_FS_SELECTOR = 0x00000808,
176 GUEST_GS_SELECTOR = 0x0000080a,
177 GUEST_LDTR_SELECTOR = 0x0000080c,
178 GUEST_TR_SELECTOR = 0x0000080e,
179 GUEST_INTR_STATUS = 0x00000810,
180 GUEST_PML_INDEX = 0x00000812,
181 HOST_ES_SELECTOR = 0x00000c00,
182 HOST_CS_SELECTOR = 0x00000c02,
183 HOST_SS_SELECTOR = 0x00000c04,
184 HOST_DS_SELECTOR = 0x00000c06,
185 HOST_FS_SELECTOR = 0x00000c08,
186 HOST_GS_SELECTOR = 0x00000c0a,
187 HOST_TR_SELECTOR = 0x00000c0c,
188 IO_BITMAP_A = 0x00002000,
189 IO_BITMAP_A_HIGH = 0x00002001,
190 IO_BITMAP_B = 0x00002002,
191 IO_BITMAP_B_HIGH = 0x00002003,
192 MSR_BITMAP = 0x00002004,
193 MSR_BITMAP_HIGH = 0x00002005,
194 VM_EXIT_MSR_STORE_ADDR = 0x00002006,
195 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
196 VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
197 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
198 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
199 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
200 PML_ADDRESS = 0x0000200e,
201 PML_ADDRESS_HIGH = 0x0000200f,
202 TSC_OFFSET = 0x00002010,
203 TSC_OFFSET_HIGH = 0x00002011,
204 VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
205 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
206 APIC_ACCESS_ADDR = 0x00002014,
207 APIC_ACCESS_ADDR_HIGH = 0x00002015,
208 POSTED_INTR_DESC_ADDR = 0x00002016,
209 POSTED_INTR_DESC_ADDR_HIGH = 0x00002017,
210 VM_FUNCTION_CONTROL = 0x00002018,
211 VM_FUNCTION_CONTROL_HIGH = 0x00002019,
212 EPT_POINTER = 0x0000201a,
213 EPT_POINTER_HIGH = 0x0000201b,
214 EOI_EXIT_BITMAP0 = 0x0000201c,
215 EOI_EXIT_BITMAP0_HIGH = 0x0000201d,
216 EOI_EXIT_BITMAP1 = 0x0000201e,
217 EOI_EXIT_BITMAP1_HIGH = 0x0000201f,
218 EOI_EXIT_BITMAP2 = 0x00002020,
219 EOI_EXIT_BITMAP2_HIGH = 0x00002021,
220 EOI_EXIT_BITMAP3 = 0x00002022,
221 EOI_EXIT_BITMAP3_HIGH = 0x00002023,
222 EPTP_LIST_ADDRESS = 0x00002024,
223 EPTP_LIST_ADDRESS_HIGH = 0x00002025,
224 VMREAD_BITMAP = 0x00002026,
225 VMREAD_BITMAP_HIGH = 0x00002027,
226 VMWRITE_BITMAP = 0x00002028,
227 VMWRITE_BITMAP_HIGH = 0x00002029,
228 XSS_EXIT_BITMAP = 0x0000202C,
229 XSS_EXIT_BITMAP_HIGH = 0x0000202D,
230 ENCLS_EXITING_BITMAP = 0x0000202E,
231 ENCLS_EXITING_BITMAP_HIGH = 0x0000202F,
232 TSC_MULTIPLIER = 0x00002032,
233 TSC_MULTIPLIER_HIGH = 0x00002033,
234 TERTIARY_VM_EXEC_CONTROL = 0x00002034,
235 TERTIARY_VM_EXEC_CONTROL_HIGH = 0x00002035,
236 PID_POINTER_TABLE = 0x00002042,
237 PID_POINTER_TABLE_HIGH = 0x00002043,
238 GUEST_PHYSICAL_ADDRESS = 0x00002400,
239 GUEST_PHYSICAL_ADDRESS_HIGH = 0x00002401,
240 VMCS_LINK_POINTER = 0x00002800,
241 VMCS_LINK_POINTER_HIGH = 0x00002801,
242 GUEST_IA32_DEBUGCTL = 0x00002802,
243 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
244 GUEST_IA32_PAT = 0x00002804,
245 GUEST_IA32_PAT_HIGH = 0x00002805,
246 GUEST_IA32_EFER = 0x00002806,
247 GUEST_IA32_EFER_HIGH = 0x00002807,
248 GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808,
249 GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
250 GUEST_PDPTR0 = 0x0000280a,
251 GUEST_PDPTR0_HIGH = 0x0000280b,
252 GUEST_PDPTR1 = 0x0000280c,
253 GUEST_PDPTR1_HIGH = 0x0000280d,
254 GUEST_PDPTR2 = 0x0000280e,
255 GUEST_PDPTR2_HIGH = 0x0000280f,
256 GUEST_PDPTR3 = 0x00002810,
257 GUEST_PDPTR3_HIGH = 0x00002811,
258 GUEST_BNDCFGS = 0x00002812,
259 GUEST_BNDCFGS_HIGH = 0x00002813,
260 GUEST_IA32_RTIT_CTL = 0x00002814,
261 GUEST_IA32_RTIT_CTL_HIGH = 0x00002815,
262 HOST_IA32_PAT = 0x00002c00,
263 HOST_IA32_PAT_HIGH = 0x00002c01,
264 HOST_IA32_EFER = 0x00002c02,
265 HOST_IA32_EFER_HIGH = 0x00002c03,
266 HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04,
267 HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
268 PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
269 CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
270 EXCEPTION_BITMAP = 0x00004004,
271 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
272 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
273 CR3_TARGET_COUNT = 0x0000400a,
274 VM_EXIT_CONTROLS = 0x0000400c,
275 VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
276 VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
277 VM_ENTRY_CONTROLS = 0x00004012,
278 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
279 VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
280 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
281 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
282 TPR_THRESHOLD = 0x0000401c,
283 SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
284 PLE_GAP = 0x00004020,
285 PLE_WINDOW = 0x00004022,
286 NOTIFY_WINDOW = 0x00004024,
287 VM_INSTRUCTION_ERROR = 0x00004400,
288 VM_EXIT_REASON = 0x00004402,
289 VM_EXIT_INTR_INFO = 0x00004404,
290 VM_EXIT_INTR_ERROR_CODE = 0x00004406,
291 IDT_VECTORING_INFO_FIELD = 0x00004408,
292 IDT_VECTORING_ERROR_CODE = 0x0000440a,
293 VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
294 VMX_INSTRUCTION_INFO = 0x0000440e,
295 GUEST_ES_LIMIT = 0x00004800,
296 GUEST_CS_LIMIT = 0x00004802,
297 GUEST_SS_LIMIT = 0x00004804,
298 GUEST_DS_LIMIT = 0x00004806,
299 GUEST_FS_LIMIT = 0x00004808,
300 GUEST_GS_LIMIT = 0x0000480a,
301 GUEST_LDTR_LIMIT = 0x0000480c,
302 GUEST_TR_LIMIT = 0x0000480e,
303 GUEST_GDTR_LIMIT = 0x00004810,
304 GUEST_IDTR_LIMIT = 0x00004812,
305 GUEST_ES_AR_BYTES = 0x00004814,
306 GUEST_CS_AR_BYTES = 0x00004816,
307 GUEST_SS_AR_BYTES = 0x00004818,
308 GUEST_DS_AR_BYTES = 0x0000481a,
309 GUEST_FS_AR_BYTES = 0x0000481c,
310 GUEST_GS_AR_BYTES = 0x0000481e,
311 GUEST_LDTR_AR_BYTES = 0x00004820,
312 GUEST_TR_AR_BYTES = 0x00004822,
313 GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
314 GUEST_ACTIVITY_STATE = 0x00004826,
315 GUEST_SYSENTER_CS = 0x0000482A,
316 VMX_PREEMPTION_TIMER_VALUE = 0x0000482E,
317 HOST_IA32_SYSENTER_CS = 0x00004c00,
318 CR0_GUEST_HOST_MASK = 0x00006000,
319 CR4_GUEST_HOST_MASK = 0x00006002,
320 CR0_READ_SHADOW = 0x00006004,
321 CR4_READ_SHADOW = 0x00006006,
322 CR3_TARGET_VALUE0 = 0x00006008,
323 CR3_TARGET_VALUE1 = 0x0000600a,
324 CR3_TARGET_VALUE2 = 0x0000600c,
325 CR3_TARGET_VALUE3 = 0x0000600e,
326 EXIT_QUALIFICATION = 0x00006400,
327 GUEST_LINEAR_ADDRESS = 0x0000640a,
328 GUEST_CR0 = 0x00006800,
329 GUEST_CR3 = 0x00006802,
330 GUEST_CR4 = 0x00006804,
331 GUEST_ES_BASE = 0x00006806,
332 GUEST_CS_BASE = 0x00006808,
333 GUEST_SS_BASE = 0x0000680a,
334 GUEST_DS_BASE = 0x0000680c,
335 GUEST_FS_BASE = 0x0000680e,
336 GUEST_GS_BASE = 0x00006810,
337 GUEST_LDTR_BASE = 0x00006812,
338 GUEST_TR_BASE = 0x00006814,
339 GUEST_GDTR_BASE = 0x00006816,
340 GUEST_IDTR_BASE = 0x00006818,
341 GUEST_DR7 = 0x0000681a,
342 GUEST_RSP = 0x0000681c,
343 GUEST_RIP = 0x0000681e,
344 GUEST_RFLAGS = 0x00006820,
345 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
346 GUEST_SYSENTER_ESP = 0x00006824,
347 GUEST_SYSENTER_EIP = 0x00006826,
348 HOST_CR0 = 0x00006c00,
349 HOST_CR3 = 0x00006c02,
350 HOST_CR4 = 0x00006c04,
351 HOST_FS_BASE = 0x00006c06,
352 HOST_GS_BASE = 0x00006c08,
353 HOST_TR_BASE = 0x00006c0a,
354 HOST_GDTR_BASE = 0x00006c0c,
355 HOST_IDTR_BASE = 0x00006c0e,
356 HOST_IA32_SYSENTER_ESP = 0x00006c10,
357 HOST_IA32_SYSENTER_EIP = 0x00006c12,
358 HOST_RSP = 0x00006c14,
359 HOST_RIP = 0x00006c16,
365 #define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */
366 #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */
367 #define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */
368 #define INTR_INFO_UNBLOCK_NMI 0x1000 /* 12 */
369 #define INTR_INFO_VALID_MASK 0x80000000 /* 31 */
370 #define INTR_INFO_RESVD_BITS_MASK 0x7ffff000
377 #define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */
387 #define GUEST_INTR_STATE_STI 0x00000001
388 #define GUEST_INTR_STATE_MOV_SS 0x00000002
389 #define GUEST_INTR_STATE_SMI 0x00000004
390 #define GUEST_INTR_STATE_NMI 0x00000008
391 #define GUEST_INTR_STATE_ENCLAVE_INTR 0x00000010
394 #define GUEST_ACTIVITY_ACTIVE 0
402 #define CONTROL_REG_ACCESS_NUM 0x7 /* 2:0, number of control reg.*/
403 #define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */
404 #define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose reg. */
406 #define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
407 #define REG_EAX (0 << 8)
427 #define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug reg. */
428 #define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */
429 #define TYPE_MOV_TO_DR (0 << 4)
431 #define DEBUG_REG_ACCESS_REG(eq) (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
437 #define APIC_ACCESS_OFFSET 0xfff /* 11:0, offset within the APIC page */
438 #define APIC_ACCESS_TYPE 0xf000 /* 15:12, access type */
439 #define TYPE_LINEAR_APIC_INST_READ (0 << 12)
453 #define VMX_AR_TYPE_MASK 0x0f
468 #define VMX_AR_RESERVD_MASK 0xfffe0f00
470 #define TSS_PRIVATE_MEMSLOT (KVM_USER_MEM_SLOTS + 0)
475 #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR 0
496 #define VMX_VPID_INVVPID_BIT (1ull << 0) /* (32 - 32) */
503 #define VMX_EPTP_PWL_MASK 0x38ull
504 #define VMX_EPTP_PWL_4 0x18ull
505 #define VMX_EPTP_PWL_5 0x20ull
507 #define VMX_EPTP_MT_MASK 0x7ull
508 #define VMX_EPTP_MT_WB 0x6ull
509 #define VMX_EPTP_MT_UC 0x0ull
510 #define VMX_EPT_READABLE_MASK 0x1ull
511 #define VMX_EPT_WRITABLE_MASK 0x2ull
512 #define VMX_EPT_EXECUTABLE_MASK 0x4ull
537 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR 0xfffbc000ul
549 ENTRY_FAIL_DEFAULT = 0,
558 #define EPT_VIOLATION_ACC_READ_BIT 0
574 #define NOTIFY_VM_CONTEXT_INVALID BIT(0)