Lines Matching +full:architecturally +full:- +full:defined

1 /* SPDX-License-Identifier: GPL-2.0 */
47 /* AMD-specific bits */
56  *  - Deferred error interrupt type is specifiable by bank.
57  *  - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers,
59  *  - TCC bit is present in MCx_STATUS.
67  * bits 15:0.  But bit 12 is the 'F' bit, defined for corrected
70  * of uncorrected errors - so the F bit is deliberately skipped
75 /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
76 #define MCACOD_SCRUB	0x00C0	/* 0xC0-0xCF Memory Scrubbing */
92 #define MCI_ADDR_PHYSADDR	GENMASK_ULL(boot_cpu_data.x86_phys_bits - 1, 0)
219 					     u64 lapic_id) { return -EINVAL; }  in apei_smca_report_x86_error()