Lines Matching +full:add +full:- +full:pmem
1 // SPDX-License-Identifier: GPL-2.0
106 static void __init __intel_pmu_pebs_data_source_skl(bool pmem, u64 *data_source) in __intel_pmu_pebs_data_source_skl() argument
108 u64 pmem_or_l4 = pmem ? LEVEL(PMEM) : LEVEL(L4); in __intel_pmu_pebs_data_source_skl()
117 void __init intel_pmu_pebs_data_source_skl(bool pmem) in intel_pmu_pebs_data_source_skl() argument
119 __intel_pmu_pebs_data_source_skl(pmem, pebs_data_source); in intel_pmu_pebs_data_source_skl()
219 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) in precise_datala_hsw()
221 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW) in precise_datala_hsw()
232 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) { in precise_datala_hsw()
258 /* Retrieve the latency data for e-core of ADL */
264 WARN_ON_ONCE(hybrid_pmu(event->pmu)->pmu_type == hybrid_big); in __adl_latency_data_small()
267 val = hybrid_var(event->pmu, pebs_data_source)[dse]; in __adl_latency_data_small()
290 /* Retrieve the latency data for e-core of MTL */
310 * use the mapping table for bit 0-3 in load_latency_data()
312 val = hybrid_var(event->pmu, pebs_data_source)[dse.ld_dse]; in load_latency_data()
360 * use the mapping table for bit 0-3 in store_latency_data()
362 val = hybrid_var(event->pmu, pebs_data_source)[dse.st_lat_dse]; in store_latency_data()
473 * This is a cross-CPU update of the cpu_entry_area, we must shoot down in ds_update_cea()
512 struct debug_store *ds = hwev->ds; in alloc_pebs_buffer()
522 return -ENOMEM; in alloc_pebs_buffer()
532 return -ENOMEM; in alloc_pebs_buffer()
536 hwev->ds_pebs_vaddr = buffer; in alloc_pebs_buffer()
538 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer; in alloc_pebs_buffer()
539 ds->pebs_buffer_base = (unsigned long) cea; in alloc_pebs_buffer()
541 ds->pebs_index = ds->pebs_buffer_base; in alloc_pebs_buffer()
543 ds->pebs_absolute_maximum = ds->pebs_buffer_base + max; in alloc_pebs_buffer()
559 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer; in release_pebs_buffer()
561 dsfree_pages(hwev->ds_pebs_vaddr, x86_pmu.pebs_buffer_size); in release_pebs_buffer()
562 hwev->ds_pebs_vaddr = NULL; in release_pebs_buffer()
568 struct debug_store *ds = hwev->ds; in alloc_bts_buffer()
578 return -ENOMEM; in alloc_bts_buffer()
580 hwev->ds_bts_vaddr = buffer; in alloc_bts_buffer()
582 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer; in alloc_bts_buffer()
583 ds->bts_buffer_base = (unsigned long) cea; in alloc_bts_buffer()
585 ds->bts_index = ds->bts_buffer_base; in alloc_bts_buffer()
587 ds->bts_absolute_maximum = ds->bts_buffer_base + in alloc_bts_buffer()
589 ds->bts_interrupt_threshold = ds->bts_absolute_maximum - in alloc_bts_buffer()
603 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer; in release_bts_buffer()
605 dsfree_pages(hwev->ds_bts_vaddr, BTS_BUFFER_SIZE); in release_bts_buffer()
606 hwev->ds_bts_vaddr = NULL; in release_bts_buffer()
611 struct debug_store *ds = &get_cpu_entry_area(cpu)->cpu_debug_store; in alloc_ds_buffer()
743 if (!cpuc->ds) in intel_pmu_disable_bts()
758 struct debug_store *ds = cpuc->ds; in intel_pmu_drain_bts_buffer()
764 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS]; in intel_pmu_drain_bts_buffer()
778 base = (struct bts_record *)(unsigned long)ds->bts_buffer_base; in intel_pmu_drain_bts_buffer()
779 top = (struct bts_record *)(unsigned long)ds->bts_index; in intel_pmu_drain_bts_buffer()
786 ds->bts_index = ds->bts_buffer_base; in intel_pmu_drain_bts_buffer()
788 perf_sample_data_init(&data, 0, event->hw.last_period); in intel_pmu_drain_bts_buffer()
806 if (event->attr.exclude_kernel && in intel_pmu_drain_bts_buffer()
807 (kernel_ip(at->from) || kernel_ip(at->to))) in intel_pmu_drain_bts_buffer()
821 header.size * (top - base - skip))) in intel_pmu_drain_bts_buffer()
826 if (event->attr.exclude_kernel && in intel_pmu_drain_bts_buffer()
827 (kernel_ip(at->from) || kernel_ip(at->to))) in intel_pmu_drain_bts_buffer()
830 data.ip = at->from; in intel_pmu_drain_bts_buffer()
831 data.addr = at->to; in intel_pmu_drain_bts_buffer()
839 event->hw.interrupts++; in intel_pmu_drain_bts_buffer()
840 event->pending_kill = POLL_IN; in intel_pmu_drain_bts_buffer()
1090 struct event_constraint *pebs_constraints = hybrid(event->pmu, pebs_constraints); in intel_pebs_constraints()
1093 if (!event->attr.precise_ip) in intel_pebs_constraints()
1098 if (constraint_match(c, event->hw.config)) { in intel_pebs_constraints()
1099 event->hw.flags |= c->flags; in intel_pebs_constraints()
1116 * We need the sched_task callback even for per-cpu events when we use
1122 if (cpuc->n_pebs == cpuc->n_pebs_via_pt) in pebs_needs_sched_cb()
1125 return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs); in pebs_needs_sched_cb()
1138 struct debug_store *ds = cpuc->ds; in pebs_update_threshold()
1139 int max_pebs_events = hybrid(cpuc->pmu, max_pebs_events); in pebs_update_threshold()
1140 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed); in pebs_update_threshold()
1144 if (cpuc->n_pebs_via_pt) in pebs_update_threshold()
1152 if (cpuc->n_pebs == cpuc->n_large_pebs) { in pebs_update_threshold()
1153 threshold = ds->pebs_absolute_maximum - in pebs_update_threshold()
1154 reserved * cpuc->pebs_record_size; in pebs_update_threshold()
1156 threshold = ds->pebs_buffer_base + cpuc->pebs_record_size; in pebs_update_threshold()
1159 ds->pebs_interrupt_threshold = threshold; in pebs_update_threshold()
1165 u64 pebs_data_cfg = cpuc->pebs_data_cfg; in adaptive_pebs_record_size_update()
1177 cpuc->pebs_record_size = sz; in adaptive_pebs_record_size_update()
1188 struct perf_event_attr *attr = &event->attr; in pebs_update_adaptive_cfg()
1189 u64 sample_type = attr->sample_type; in pebs_update_adaptive_cfg()
1194 attr->precise_ip > 1) in pebs_update_adaptive_cfg()
1207 (attr->sample_regs_intr & PEBS_GP_REGS); in pebs_update_adaptive_cfg()
1210 ((attr->config & INTEL_ARCH_EVENT_MASK) == in pebs_update_adaptive_cfg()
1213 if (gprs || (attr->precise_ip < 2) || tsx_weight) in pebs_update_adaptive_cfg()
1217 (attr->sample_regs_intr & PERF_REG_EXTENDED_MASK)) in pebs_update_adaptive_cfg()
1226 ((x86_pmu.lbr_nr-1) << PEBS_DATACFG_LBR_SHIFT); in pebs_update_adaptive_cfg()
1234 struct perf_event *event, bool add) in pebs_update_state() argument
1236 struct pmu *pmu = event->pmu; in pebs_update_state()
1243 if (cpuc->n_pebs == 1) in pebs_update_state()
1244 cpuc->pebs_data_cfg = PEBS_UPDATE_DS_SW; in pebs_update_state()
1252 cpuc->pebs_data_cfg |= PEBS_UPDATE_DS_SW; in pebs_update_state()
1259 if (x86_pmu.intel_cap.pebs_baseline && add) { in pebs_update_state()
1266 if (pebs_data_cfg & ~cpuc->pebs_data_cfg) in pebs_update_state()
1267 cpuc->pebs_data_cfg |= pebs_data_cfg | PEBS_UPDATE_DS_SW; in pebs_update_state()
1274 struct hw_perf_event *hwc = &event->hw; in intel_pmu_pebs_add()
1277 cpuc->n_pebs++; in intel_pmu_pebs_add()
1278 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS) in intel_pmu_pebs_add()
1279 cpuc->n_large_pebs++; in intel_pmu_pebs_add()
1280 if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT) in intel_pmu_pebs_add()
1281 cpuc->n_pebs_via_pt++; in intel_pmu_pebs_add()
1293 if (!(cpuc->pebs_enabled & ~PEBS_VIA_PT_MASK)) in intel_pmu_pebs_via_pt_disable()
1294 cpuc->pebs_enabled &= ~PEBS_VIA_PT_MASK; in intel_pmu_pebs_via_pt_disable()
1300 struct hw_perf_event *hwc = &event->hw; in intel_pmu_pebs_via_pt_enable()
1301 struct debug_store *ds = cpuc->ds; in intel_pmu_pebs_via_pt_enable()
1302 u64 value = ds->pebs_event_reset[hwc->idx]; in intel_pmu_pebs_via_pt_enable()
1304 unsigned int idx = hwc->idx; in intel_pmu_pebs_via_pt_enable()
1309 if (!(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS)) in intel_pmu_pebs_via_pt_enable()
1310 cpuc->pebs_enabled |= PEBS_PMI_AFTER_EACH_RECORD; in intel_pmu_pebs_via_pt_enable()
1312 cpuc->pebs_enabled |= PEBS_OUTPUT_PT; in intel_pmu_pebs_via_pt_enable()
1314 if (hwc->idx >= INTEL_PMC_IDX_FIXED) { in intel_pmu_pebs_via_pt_enable()
1316 idx = hwc->idx - INTEL_PMC_IDX_FIXED; in intel_pmu_pebs_via_pt_enable()
1318 value = ds->pebs_event_reset[MAX_PEBS_EVENTS_FMT4 + idx]; in intel_pmu_pebs_via_pt_enable()
1320 value = ds->pebs_event_reset[MAX_PEBS_EVENTS + idx]; in intel_pmu_pebs_via_pt_enable()
1327 if (cpuc->n_pebs == cpuc->n_large_pebs && in intel_pmu_drain_large_pebs()
1328 cpuc->n_pebs != cpuc->n_pebs_via_pt) in intel_pmu_drain_large_pebs()
1335 u64 pebs_data_cfg = cpuc->pebs_data_cfg & ~PEBS_UPDATE_DS_SW; in intel_pmu_pebs_enable()
1336 struct hw_perf_event *hwc = &event->hw; in intel_pmu_pebs_enable()
1337 struct debug_store *ds = cpuc->ds; in intel_pmu_pebs_enable()
1338 unsigned int idx = hwc->idx; in intel_pmu_pebs_enable()
1340 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT; in intel_pmu_pebs_enable()
1342 cpuc->pebs_enabled |= 1ULL << hwc->idx; in intel_pmu_pebs_enable()
1344 if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) && (x86_pmu.version < 5)) in intel_pmu_pebs_enable()
1345 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32); in intel_pmu_pebs_enable()
1346 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST) in intel_pmu_pebs_enable()
1347 cpuc->pebs_enabled |= 1ULL << 63; in intel_pmu_pebs_enable()
1350 hwc->config |= ICL_EVENTSEL_ADAPTIVE; in intel_pmu_pebs_enable()
1351 if (pebs_data_cfg != cpuc->active_pebs_data_cfg) { in intel_pmu_pebs_enable()
1360 cpuc->active_pebs_data_cfg = pebs_data_cfg; in intel_pmu_pebs_enable()
1363 if (cpuc->pebs_data_cfg & PEBS_UPDATE_DS_SW) { in intel_pmu_pebs_enable()
1364 cpuc->pebs_data_cfg = pebs_data_cfg; in intel_pmu_pebs_enable()
1370 idx = MAX_PEBS_EVENTS_FMT4 + (idx - INTEL_PMC_IDX_FIXED); in intel_pmu_pebs_enable()
1372 idx = MAX_PEBS_EVENTS + (idx - INTEL_PMC_IDX_FIXED); in intel_pmu_pebs_enable()
1376 * Use auto-reload if possible to save a MSR write in the PMI. in intel_pmu_pebs_enable()
1379 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) { in intel_pmu_pebs_enable()
1380 ds->pebs_event_reset[idx] = in intel_pmu_pebs_enable()
1381 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask; in intel_pmu_pebs_enable()
1383 ds->pebs_event_reset[idx] = 0; in intel_pmu_pebs_enable()
1392 struct hw_perf_event *hwc = &event->hw; in intel_pmu_pebs_del()
1395 cpuc->n_pebs--; in intel_pmu_pebs_del()
1396 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS) in intel_pmu_pebs_del()
1397 cpuc->n_large_pebs--; in intel_pmu_pebs_del()
1398 if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT) in intel_pmu_pebs_del()
1399 cpuc->n_pebs_via_pt--; in intel_pmu_pebs_del()
1407 struct hw_perf_event *hwc = &event->hw; in intel_pmu_pebs_disable()
1411 cpuc->pebs_enabled &= ~(1ULL << hwc->idx); in intel_pmu_pebs_disable()
1413 if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) && in intel_pmu_pebs_disable()
1415 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32)); in intel_pmu_pebs_disable()
1416 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST) in intel_pmu_pebs_disable()
1417 cpuc->pebs_enabled &= ~(1ULL << 63); in intel_pmu_pebs_disable()
1421 if (cpuc->enabled) in intel_pmu_pebs_disable()
1422 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); in intel_pmu_pebs_disable()
1424 hwc->config |= ARCH_PERFMON_EVENTSEL_INT; in intel_pmu_pebs_disable()
1431 if (cpuc->pebs_enabled) in intel_pmu_pebs_enable_all()
1432 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled); in intel_pmu_pebs_enable_all()
1439 if (cpuc->pebs_enabled) in intel_pmu_pebs_disable_all()
1446 unsigned long from = cpuc->lbr_entries[0].from; in intel_pmu_pebs_fixup_ip()
1447 unsigned long old_to, to = cpuc->lbr_entries[0].to; in intel_pmu_pebs_fixup_ip()
1448 unsigned long ip = regs->ip; in intel_pmu_pebs_fixup_ip()
1462 if (!cpuc->lbr_stack.nr || !from || !to) in intel_pmu_pebs_fixup_ip()
1475 if ((ip - to) > PEBS_FIXUP_SIZE) in intel_pmu_pebs_fixup_ip()
1486 size = ip - to; in intel_pmu_pebs_fixup_ip()
1521 size -= insn.length; in intel_pmu_pebs_fixup_ip()
1558 return ((struct pebs_record_nhm *)n)->status; in get_pebs_status()
1559 return ((struct pebs_basic *)n)->applicable_counters; in get_pebs_status()
1570 int fl = event->hw.flags; in get_data_src()
1590 /* Converting to a user-defined clock is not supported yet. */ in setup_pebs_time()
1591 if (event->attr.use_clockid != 0) in setup_pebs_time()
1603 data->time = native_sched_clock_from_tsc(tsc) + __sched_clock_offset; in setup_pebs_time()
1604 data->sample_flags |= PERF_SAMPLE_TIME; in setup_pebs_time()
1628 sample_type = event->attr.sample_type; in setup_pebs_fixed_sample_data()
1629 fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT; in setup_pebs_fixed_sample_data()
1631 perf_sample_data_init(data, 0, event->hw.last_period); in setup_pebs_fixed_sample_data()
1633 data->period = event->hw.last_period; in setup_pebs_fixed_sample_data()
1636 * Use latency for weight (only avail with PEBS-LL) in setup_pebs_fixed_sample_data()
1639 data->weight.full = pebs->lat; in setup_pebs_fixed_sample_data()
1640 data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE; in setup_pebs_fixed_sample_data()
1647 data->data_src.val = get_data_src(event, pebs->dse); in setup_pebs_fixed_sample_data()
1648 data->sample_flags |= PERF_SAMPLE_DATA_SRC; in setup_pebs_fixed_sample_data()
1674 regs->flags = pebs->flags & ~PERF_EFLAGS_EXACT; in setup_pebs_fixed_sample_data()
1677 regs->ax = pebs->ax; in setup_pebs_fixed_sample_data()
1678 regs->bx = pebs->bx; in setup_pebs_fixed_sample_data()
1679 regs->cx = pebs->cx; in setup_pebs_fixed_sample_data()
1680 regs->dx = pebs->dx; in setup_pebs_fixed_sample_data()
1681 regs->si = pebs->si; in setup_pebs_fixed_sample_data()
1682 regs->di = pebs->di; in setup_pebs_fixed_sample_data()
1684 regs->bp = pebs->bp; in setup_pebs_fixed_sample_data()
1685 regs->sp = pebs->sp; in setup_pebs_fixed_sample_data()
1688 regs->r8 = pebs->r8; in setup_pebs_fixed_sample_data()
1689 regs->r9 = pebs->r9; in setup_pebs_fixed_sample_data()
1690 regs->r10 = pebs->r10; in setup_pebs_fixed_sample_data()
1691 regs->r11 = pebs->r11; in setup_pebs_fixed_sample_data()
1692 regs->r12 = pebs->r12; in setup_pebs_fixed_sample_data()
1693 regs->r13 = pebs->r13; in setup_pebs_fixed_sample_data()
1694 regs->r14 = pebs->r14; in setup_pebs_fixed_sample_data()
1695 regs->r15 = pebs->r15; in setup_pebs_fixed_sample_data()
1699 if (event->attr.precise_ip > 1) { in setup_pebs_fixed_sample_data()
1702 * (real IP) which fixes the off-by-1 skid in hardware. in setup_pebs_fixed_sample_data()
1706 set_linear_ip(regs, pebs->real_ip); in setup_pebs_fixed_sample_data()
1707 regs->flags |= PERF_EFLAGS_EXACT; in setup_pebs_fixed_sample_data()
1709 /* Otherwise, use PEBS off-by-1 IP: */ in setup_pebs_fixed_sample_data()
1710 set_linear_ip(regs, pebs->ip); in setup_pebs_fixed_sample_data()
1713 * With precise_ip >= 2, try to fix up the off-by-1 IP in setup_pebs_fixed_sample_data()
1715 * corrects regs->ip and calls set_linear_ip() on regs: in setup_pebs_fixed_sample_data()
1718 regs->flags |= PERF_EFLAGS_EXACT; in setup_pebs_fixed_sample_data()
1722 * When precise_ip == 1, return the PEBS off-by-1 IP, in setup_pebs_fixed_sample_data()
1725 set_linear_ip(regs, pebs->ip); in setup_pebs_fixed_sample_data()
1731 data->addr = pebs->dla; in setup_pebs_fixed_sample_data()
1732 data->sample_flags |= PERF_SAMPLE_ADDR; in setup_pebs_fixed_sample_data()
1738 data->weight.full = intel_get_tsx_weight(pebs->tsx_tuning); in setup_pebs_fixed_sample_data()
1739 data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE; in setup_pebs_fixed_sample_data()
1742 data->txn = intel_get_tsx_transaction(pebs->tsx_tuning, in setup_pebs_fixed_sample_data()
1743 pebs->ax); in setup_pebs_fixed_sample_data()
1744 data->sample_flags |= PERF_SAMPLE_TRANSACTION; in setup_pebs_fixed_sample_data()
1755 setup_pebs_time(event, data, pebs->tsc); in setup_pebs_fixed_sample_data()
1758 perf_sample_save_brstack(data, event, &cpuc->lbr_stack, NULL); in setup_pebs_fixed_sample_data()
1764 regs->ax = gprs->ax; in adaptive_pebs_save_regs()
1765 regs->bx = gprs->bx; in adaptive_pebs_save_regs()
1766 regs->cx = gprs->cx; in adaptive_pebs_save_regs()
1767 regs->dx = gprs->dx; in adaptive_pebs_save_regs()
1768 regs->si = gprs->si; in adaptive_pebs_save_regs()
1769 regs->di = gprs->di; in adaptive_pebs_save_regs()
1770 regs->bp = gprs->bp; in adaptive_pebs_save_regs()
1771 regs->sp = gprs->sp; in adaptive_pebs_save_regs()
1773 regs->r8 = gprs->r8; in adaptive_pebs_save_regs()
1774 regs->r9 = gprs->r9; in adaptive_pebs_save_regs()
1775 regs->r10 = gprs->r10; in adaptive_pebs_save_regs()
1776 regs->r11 = gprs->r11; in adaptive_pebs_save_regs()
1777 regs->r12 = gprs->r12; in adaptive_pebs_save_regs()
1778 regs->r13 = gprs->r13; in adaptive_pebs_save_regs()
1779 regs->r14 = gprs->r14; in adaptive_pebs_save_regs()
1780 regs->r15 = gprs->r15; in adaptive_pebs_save_regs()
1810 perf_regs->xmm_regs = NULL; in setup_pebs_adaptive_sample_data()
1812 sample_type = event->attr.sample_type; in setup_pebs_adaptive_sample_data()
1813 format_size = basic->format_size; in setup_pebs_adaptive_sample_data()
1814 perf_sample_data_init(data, 0, event->hw.last_period); in setup_pebs_adaptive_sample_data()
1815 data->period = event->hw.last_period; in setup_pebs_adaptive_sample_data()
1817 setup_pebs_time(event, data, basic->tsc); in setup_pebs_adaptive_sample_data()
1830 set_linear_ip(regs, basic->ip); in setup_pebs_adaptive_sample_data()
1831 regs->flags = PERF_EFLAGS_EXACT; in setup_pebs_adaptive_sample_data()
1834 data->weight.var3_w = format_size >> PEBS_RETIRE_LATENCY_OFFSET & PEBS_LATENCY_MASK; in setup_pebs_adaptive_sample_data()
1838 * But PERF_SAMPLE_TRANSACTION needs gprs->ax. in setup_pebs_adaptive_sample_data()
1850 if (event->attr.precise_ip < 2) { in setup_pebs_adaptive_sample_data()
1851 set_linear_ip(regs, gprs->ip); in setup_pebs_adaptive_sample_data()
1852 regs->flags &= ~PERF_EFLAGS_EXACT; in setup_pebs_adaptive_sample_data()
1861 u64 weight = meminfo->latency; in setup_pebs_adaptive_sample_data()
1864 data->weight.var2_w = weight & PEBS_LATENCY_MASK; in setup_pebs_adaptive_sample_data()
1874 data->weight.full = weight ?: in setup_pebs_adaptive_sample_data()
1875 intel_get_tsx_weight(meminfo->tsx_tuning); in setup_pebs_adaptive_sample_data()
1877 data->weight.var1_dw = (u32)(weight & PEBS_LATENCY_MASK) ?: in setup_pebs_adaptive_sample_data()
1878 intel_get_tsx_weight(meminfo->tsx_tuning); in setup_pebs_adaptive_sample_data()
1880 data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE; in setup_pebs_adaptive_sample_data()
1884 data->data_src.val = get_data_src(event, meminfo->aux); in setup_pebs_adaptive_sample_data()
1885 data->sample_flags |= PERF_SAMPLE_DATA_SRC; in setup_pebs_adaptive_sample_data()
1889 data->addr = meminfo->address; in setup_pebs_adaptive_sample_data()
1890 data->sample_flags |= PERF_SAMPLE_ADDR; in setup_pebs_adaptive_sample_data()
1894 data->txn = intel_get_tsx_transaction(meminfo->tsx_tuning, in setup_pebs_adaptive_sample_data()
1895 gprs ? gprs->ax : 0); in setup_pebs_adaptive_sample_data()
1896 data->sample_flags |= PERF_SAMPLE_TRANSACTION; in setup_pebs_adaptive_sample_data()
1904 perf_regs->xmm_regs = xmm->xmm; in setup_pebs_adaptive_sample_data()
1922 (u64)(next_record - __pebs), in setup_pebs_adaptive_sample_data()
1923 basic->format_size); in setup_pebs_adaptive_sample_data()
1943 for (at = base; at < top; at += cpuc->pebs_record_size) { in get_next_pebs_record_by_bit()
1954 /* clear non-PEBS bit and re-check */ in get_next_pebs_record_by_bit()
1955 pebs_status = status & cpuc->pebs_enabled; in get_next_pebs_record_by_bit()
1966 WARN_ON(!(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)); in intel_pmu_auto_reload_read()
1968 perf_pmu_disable(event->pmu); in intel_pmu_auto_reload_read()
1970 perf_pmu_enable(event->pmu); in intel_pmu_auto_reload_read()
1974 * Special variant of intel_pmu_save_and_restart() for auto-reload.
1979 struct hw_perf_event *hwc = &event->hw; in intel_pmu_save_and_restart_reload()
1980 int shift = 64 - x86_pmu.cntval_bits; in intel_pmu_save_and_restart_reload()
1981 u64 period = hwc->sample_period; in intel_pmu_save_and_restart_reload()
1992 prev_raw_count = local64_read(&hwc->prev_count); in intel_pmu_save_and_restart_reload()
1993 rdpmcl(hwc->event_base_rdpmc, new_raw_count); in intel_pmu_save_and_restart_reload()
1994 local64_set(&hwc->prev_count, new_raw_count); in intel_pmu_save_and_restart_reload()
2000 * [-period, 0] in intel_pmu_save_and_restart_reload()
2004 * A) value2 - value1; in intel_pmu_save_and_restart_reload()
2007 * B) (0 - value1) + (value2 - (-period)); in intel_pmu_save_and_restart_reload()
2010 * C) (0 - value1) + (n - 1) * (period) + (value2 - (-period)); in intel_pmu_save_and_restart_reload()
2021 * value2 - value1 + n * period in intel_pmu_save_and_restart_reload()
2025 local64_add(new - old + count * period, &event->count); in intel_pmu_save_and_restart_reload()
2027 local64_set(&hwc->period_left, -new); in intel_pmu_save_and_restart_reload()
2047 struct hw_perf_event *hwc = &event->hw; in __intel_pmu_pebs_event()
2053 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) { in __intel_pmu_pebs_event()
2055 * Now, auto-reload is only enabled in fixed period mode. in __intel_pmu_pebs_event()
2056 * The reload value is always hwc->sample_period. in __intel_pmu_pebs_event()
2057 * May need to change it, if auto-reload is enabled in in __intel_pmu_pebs_event()
2070 at += cpuc->pebs_record_size; in __intel_pmu_pebs_event()
2072 count--; in __intel_pmu_pebs_event()
2078 * The PEBS records may be drained in the non-overflow context, in __intel_pmu_pebs_event()
2097 struct debug_store *ds = cpuc->ds; in intel_pmu_drain_pebs_core()
2098 struct perf_event *event = cpuc->events[0]; /* PMC0 only */ in intel_pmu_drain_pebs_core()
2105 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base; in intel_pmu_drain_pebs_core()
2106 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index; in intel_pmu_drain_pebs_core()
2111 ds->pebs_index = ds->pebs_buffer_base; in intel_pmu_drain_pebs_core()
2113 if (!test_bit(0, cpuc->active_mask)) in intel_pmu_drain_pebs_core()
2118 if (!event->attr.precise_ip) in intel_pmu_drain_pebs_core()
2121 n = top - at; in intel_pmu_drain_pebs_core()
2123 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) in intel_pmu_drain_pebs_core()
2139 * for auto-reload event in pmu::read(). There are no in intel_pmu_pebs_event_update_no_drain()
2142 * update the event->count for this case. in intel_pmu_pebs_event_update_no_drain()
2144 for_each_set_bit(bit, (unsigned long *)&cpuc->pebs_enabled, size) { in intel_pmu_pebs_event_update_no_drain()
2145 event = cpuc->events[bit]; in intel_pmu_pebs_event_update_no_drain()
2146 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD) in intel_pmu_pebs_event_update_no_drain()
2154 struct debug_store *ds = cpuc->ds; in intel_pmu_drain_pebs_nhm()
2165 base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base; in intel_pmu_drain_pebs_nhm()
2166 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index; in intel_pmu_drain_pebs_nhm()
2168 ds->pebs_index = ds->pebs_buffer_base; in intel_pmu_drain_pebs_nhm()
2170 mask = (1ULL << x86_pmu.max_pebs_events) - 1; in intel_pmu_drain_pebs_nhm()
2173 mask |= ((1ULL << x86_pmu.num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED; in intel_pmu_drain_pebs_nhm()
2186 pebs_status = p->status & cpuc->pebs_enabled; in intel_pmu_drain_pebs_nhm()
2205 if (!pebs_status && cpuc->pebs_enabled && in intel_pmu_drain_pebs_nhm()
2206 !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1))) in intel_pmu_drain_pebs_nhm()
2207 pebs_status = p->status = cpuc->pebs_enabled; in intel_pmu_drain_pebs_nhm()
2219 * If these events include one PEBS and multiple non-PEBS in intel_pmu_drain_pebs_nhm()
2242 event = cpuc->events[bit]; in intel_pmu_drain_pebs_nhm()
2246 if (WARN_ON_ONCE(!event->attr.precise_ip)) in intel_pmu_drain_pebs_nhm()
2269 int max_pebs_events = hybrid(cpuc->pmu, max_pebs_events); in intel_pmu_drain_pebs_icl()
2270 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed); in intel_pmu_drain_pebs_icl()
2271 struct debug_store *ds = cpuc->ds; in intel_pmu_drain_pebs_icl()
2280 base = (struct pebs_basic *)(unsigned long)ds->pebs_buffer_base; in intel_pmu_drain_pebs_icl()
2281 top = (struct pebs_basic *)(unsigned long)ds->pebs_index; in intel_pmu_drain_pebs_icl()
2283 ds->pebs_index = ds->pebs_buffer_base; in intel_pmu_drain_pebs_icl()
2285 mask = ((1ULL << max_pebs_events) - 1) | in intel_pmu_drain_pebs_icl()
2286 (((1ULL << num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED); in intel_pmu_drain_pebs_icl()
2294 for (at = base; at < top; at += cpuc->pebs_record_size) { in intel_pmu_drain_pebs_icl()
2297 pebs_status = get_pebs_status(at) & cpuc->pebs_enabled; in intel_pmu_drain_pebs_icl()
2308 event = cpuc->events[bit]; in intel_pmu_drain_pebs_icl()
2312 if (WARN_ON_ONCE(!event->attr.precise_ip)) in intel_pmu_drain_pebs_icl()
2340 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-'; in intel_ds_init()
2394 pebs_qual = "-baseline"; in intel_ds_init()
2395 x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_EXTENDED_REGS; in intel_ds_init()
2409 pr_cont("PEBS-via-PT, "); in intel_ds_init()
2410 x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_AUX_OUTPUT; in intel_ds_init()