events/amd/core.c

12 #include <asm/nmi.h>
665  * When a PMC counter overflows, an NMI is used to process the event and
666  * reset the counter. NMI latency can result in the counter being updated
667  * before the NMI can run, which can result in what appear to be spurious
668  * NMIs. This function is intended to wait for the NMI to run and reset
669  * the counter to avoid possible unhandled NMI messages.
697 	 * This shouldn't be called from NMI context, but add a safeguard here  in amd_pmu_check_overflow()
698 	 * to return, since if we're in NMI context we can't wait for an NMI  in amd_pmu_check_overflow()
706 	 * NMI if it has overflowed. This relies on the fact that all active  in amd_pmu_check_overflow()
770 	 * This can be called from NMI context (via x86_pmu_stop). The counter  in amd_pmu_disable_event()
772 	 * by the NMI if we're already in the NMI. And the NMI latency support  in amd_pmu_disable_event()
773 	 * below will take care of any pending NMI that might have been  in amd_pmu_disable_event()
818  * Because of NMI latency, if multiple PMC counters are active or other sources
819  * of NMIs are received, the perf NMI handler can handle one or more overflowed
820  * PMC counters outside of the NMI associated with the PMC overflow. If the NMI
821  * doesn't arrive at the LAPIC in time to become a pending NMI, then the kernel
822  * back-to-back NMI support won't be active. This PMC handler needs to take into
823  * account that this can occur, otherwise this could result in unknown NMI
824  * messages being issued. Examples of this is PMC overflow while in the NMI
826  * other source of an NMI.
828  * Attempt to mitigate this by creating an NMI window in which un-handled NMIs
832  * handled a counter. When an un-handled NMI is received, it will be claimed
1346 	/* Avoid calculating the value each time in the NMI handler */  in amd_core_pmu_init()