x86/entry/entry_64_compat.S

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * Compatibility mode system call entry point for x86-64.
5  * Copyright 2000-2002 Andi Kleen, SuSE Labs.
7 #include <asm/asm-offsets.h>
16 #include <asm/nospec-branch.h>
25  * 32-bit SYSENTER entry.
27  * 32-bit system calls through the vDSO's __kernel_vsyscall enter here
28  * on 64-bit kernels running on Intel CPUs.
33  * never happened in any of Google's Bionic versions -- it only happened
34  * in a narrow range of Intel-provided versions.
44  * ecx  arg2
64 	pushq	$__USER_DS		/* pt_regs->ss */
65 	pushq	$0			/* pt_regs->sp = 0 (placeholder) */
69 	 * off, but we need pt_regs->flags to have IF set.  Second, if TS
73 	pushfq				/* pt_regs->flags (except IF = 0) */
74 	pushq	$__USER32_CS		/* pt_regs->cs */
75 	pushq	$0			/* pt_regs->ip = 0 (placeholder) */
80 	 * the saved RAX contains a 32-bit number when we're invoking a 32-bit
81 	 * syscall.  Just in case the high bits are nonzero, zero-extend
87 	pushq	%rax			/* pt_regs->orig_ax */
88 	PUSH_AND_CLEAR_REGS rax=$-ENOSYS
103 	 * If TF is set, we will single-step all the way to here -- do_debug
105 	 * single-stepping in general.  This allows us to avoid having
107 	 * forces us to single-step through the SYSENTER entry code.)
110 	 * out-of-line as an optimization: NT is unlikely to be set in the
113 	 * not-taken and therefore its instructions won't be fetched.
131  * 32-bit SYSCALL entry.
133  * 32-bit system calls through the vDSO's __kernel_vsyscall enter here
134  * on 64-bit kernels running on AMD CPUs.
140  *  - The calling convention for SYSCALL has changed several times without
143  *  - Prior to the in-kernel X86_BUG_SYSRET_SS_ATTRS fixup, anything
147  *  - Most programmers do not directly target AMD CPUs, and the 32-bit
149  *    CPUs, Linux disables the SYSCALL instruction on 32-bit kernels
150  *    because the SYSCALL instruction in legacy/native 32-bit mode (as
154  * 32-bit SYSCALL saves RIP to RCX, clears RFLAGS.RF, then saves
160  * Note: RFLAGS saving+masking-with-MSR happens only in Long mode
161  * (in legacy 32-bit mode, IF, RF and VM bits are cleared and that's it).
168  * ecx  return address
196 	pushq	$__USER_DS		/* pt_regs->ss */
197 	pushq	%r8			/* pt_regs->sp */
198 	pushq	%r11			/* pt_regs->flags */
199 	pushq	$__USER32_CS		/* pt_regs->cs */
200 	pushq	%rcx			/* pt_regs->ip */
203 	pushq	%rax			/* pt_regs->orig_ax */
204 	PUSH_AND_CLEAR_REGS rcx=%rbp rax=$-ENOSYS
228 	movq	RBX(%rsp), %rbx		/* pt_regs->rbx */
229 	movq	RBP(%rsp), %rbp		/* pt_regs->rbp */
230 	movq	EFLAGS(%rsp), %r11	/* pt_regs->flags (in r11) */
231 	movq	RIP(%rsp), %rcx		/* pt_regs->ip (in rcx) */
232 	addq	$RAX, %rsp		/* Skip r8-r15 */
233 	popq	%rax			/* pt_regs->rax */
234 	popq	%rdx			/* Skip pt_regs->cx */
235 	popq	%rdx			/* pt_regs->dx */
236 	popq	%rsi			/* pt_regs->si */
237 	popq	%rdi			/* pt_regs->di */
242          *  EIP = ECX
247 	 * ECX will not match pt_regs->cx, but we're returning to a vDSO
250 	 * R12-R15 are callee-saved, so they contain whatever was in them
252 	 * code.  We zero R8-R10 to avoid info leaks.
254 	movq	RSP-ORIG_RAX(%rsp), %rsp
259 	 * The original userspace %rsp (RSP-ORIG_RAX(%rsp)) is stored