include/asm/tsb.h

1 /* SPDX-License-Identifier: GPL-2.0 */
6  * power-of-2 sized table of TAG/PTE pairs.  The cpu precomputes
26  * Each 16-byte slot of the TSB is the 8-byte tag and then the 8-byte
30  * -------------------------------------------------
31  * |  -  |  CONTEXT |  -  |    VADDR bits 63:22    |
32  * -------------------------------------------------
35  * But actually, since we use per-mm TSB's, we zero out the CONTEXT
49 #define TSB_TAG_LOCK_HIGH	(1 << (TSB_TAG_LOCK_BIT - 32))
52 #define TSB_TAG_INVALID_HIGH	(1 << (TSB_TAG_INVALID_BIT - 32))
55  * those if possible so we don't need to hard-lock the TSB mapping
77 #define TSB_LOAD_QUAD(TSB, REG)	\  argument
78 661:	ldda		[TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
81 	ldda		[TSB] ASI_QUAD_LDD_PHYS, REG; \
82 	ldda		[TSB] ASI_QUAD_LDD_PHYS_4V, REG; \
85 #define TSB_LOAD_TAG_HIGH(TSB, REG) \  argument
86 661:	lduwa		[TSB] ASI_N, REG; \
89 	lduwa		[TSB] ASI_PHYS_USE_EC, REG; \
92 #define TSB_LOAD_TAG(TSB, REG) \  argument
93 661:	ldxa		[TSB] ASI_N, REG; \
96 	ldxa		[TSB] ASI_PHYS_USE_EC, REG; \
148 	 * page table level where we saw the huge page mapping, but
159 	sllx		VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
160 	srlx		REG2, 64 - PAGE_SHIFT, REG2; \
164 	 sllx		VADDR, 64 - (PUD_SHIFT + PUD_BITS), REG2; \
165 	srlx		REG2, 64 - PAGE_SHIFT, REG2; \
176 	sllx		VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
177 	srlx		REG2, 64 - PAGE_SHIFT, REG2; \
191 698:	sllx		VADDR, 64 - PMD_SHIFT, REG2; \
192 	srlx		REG2, 64 - PAGE_SHIFT, REG2; \
272 	sllx		VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
273 	srlx		REG2, 64 - PAGE_SHIFT, REG2; \
277 	 sllx		VADDR, 64 - (PUD_SHIFT + PUD_BITS), REG2; \
278 	srlx		REG2, 64 - PAGE_SHIFT, REG2; \
283 	 sllx		VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
284 	srlx		REG2, 64 - PAGE_SHIFT, REG2; \
288 	sllx		VADDR, 64 - PMD_SHIFT, REG2; \
289 	srlx		REG2, 64 - PAGE_SHIFT, REG2; \
349 	and		REG2, (KERNEL_TSB_NENTRIES - 1), REG2; \
371 	and		TAG, (KERNEL_TSB4M_NENTRIES - 1), REG2; \