Lines Matching +full:1 +full:v8
31 asm volatile("std 1,%0" : "=Q" (state->fprs[1])); in __kernel_fpu_begin()
56 " la 1,%[vxrs]\n" /* load save area */ in __kernel_fpu_begin()
62 * case a vstm V8..V23 is the best instruction in __kernel_fpu_begin()
65 " jne 0f\n" /* -> save V8..V23 */ in __kernel_fpu_begin()
66 " VSTM 8,23,128,1\n" /* vstm %v8,%v23,128(%r1) */ in __kernel_fpu_begin()
72 " brc 2,1f\n" /* 10 -> save V8..V15 */ in __kernel_fpu_begin()
73 " VSTM 0,7,0,1\n" /* vstm %v0,%v7,0(%r1) */ in __kernel_fpu_begin()
75 "1: VSTM 8,15,128,1\n" /* vstm %v8,%v15,128(%r1) */ in __kernel_fpu_begin()
77 "2: VSTM 0,15,0,1\n" /* vstm %v0,%v15,0(%r1) */ in __kernel_fpu_begin()
83 " VSTM 16,23,256,1\n" /* vstm %v16,%v23,256(%r1) */ in __kernel_fpu_begin()
85 "4: VSTM 24,31,384,1\n" /* vstm %v24,%v31,384(%r1) */ in __kernel_fpu_begin()
87 "5: VSTM 0,15,0,1\n" /* vstm %v0,%v15,0(%r1) */ in __kernel_fpu_begin()
88 "6: VSTM 16,31,256,1\n" /* vstm %v16,%v31,256(%r1) */ in __kernel_fpu_begin()
92 : "1", "cc"); in __kernel_fpu_begin()
113 asm volatile("ld 1,%0" : : "Q" (state->fprs[1])); in __kernel_fpu_end()
138 " la 1,%[vxrs]\n" /* load restore area */ in __kernel_fpu_end()
144 * case a vlm V8..V23 is the best instruction in __kernel_fpu_end()
147 " jne 0f\n" /* -> restore V8..V23 */ in __kernel_fpu_end()
148 " VLM 8,23,128,1\n" /* vlm %v8,%v23,128(%r1) */ in __kernel_fpu_end()
154 " brc 2,1f\n" /* 10 -> restore V8..V15 */ in __kernel_fpu_end()
155 " VLM 0,7,0,1\n" /* vlm %v0,%v7,0(%r1) */ in __kernel_fpu_end()
157 "1: VLM 8,15,128,1\n" /* vlm %v8,%v15,128(%r1) */ in __kernel_fpu_end()
159 "2: VLM 0,15,0,1\n" /* vlm %v0,%v15,0(%r1) */ in __kernel_fpu_end()
165 " VLM 16,23,256,1\n" /* vlm %v16,%v23,256(%r1) */ in __kernel_fpu_end()
167 "4: VLM 24,31,384,1\n" /* vlm %v24,%v31,384(%r1) */ in __kernel_fpu_end()
169 "5: VLM 0,15,0,1\n" /* vlm %v0,%v15,0(%r1) */ in __kernel_fpu_end()
170 "6: VLM 16,31,256,1\n" /* vlm %v16,%v31,256(%r1) */ in __kernel_fpu_end()
174 : "1", "cc"); in __kernel_fpu_end()
185 asm volatile("lgr 1,%0\n" in __load_fpu_regs()
186 "VLM 0,15,0,1\n" in __load_fpu_regs()
187 "VLM 16,31,256,1\n" in __load_fpu_regs()
190 : "1", "cc", "memory"); in __load_fpu_regs()
193 asm volatile("ld 1,%0" : : "Q" (regs[1])); in __load_fpu_regs()
235 asm volatile("lgr 1,%0\n" in save_fpu_regs()
236 "VSTM 0,15,0,1\n" in save_fpu_regs()
237 "VSTM 16,31,256,1\n" in save_fpu_regs()
240 : "1", "cc", "memory"); in save_fpu_regs()
243 asm volatile("std 1,%0" : "=Q" (regs[1])); in save_fpu_regs()