Lines Matching +full:riscv +full:- +full:sbi

1 // SPDX-License-Identifier: GPL-2.0-only
13 #include <asm/sbi.h>
32  * Performs an icache flush for the given MM context.  RISC-V has no direct
36  * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
49 	mask = &mm->context.icache_stale_mask;  in flush_icache_mm()
62 	if (mm == current->active_mm && local) {  in flush_icache_mm()
66 		 * and scheduling this MM context on that hart.  Sending an SBI  in flush_icache_mm()
89 	if (!test_bit(PG_dcache_clean, &folio->flags)) {  in flush_icache_pte()
91 		set_bit(PG_dcache_clean, &folio->flags);  in flush_icache_pte()
134 			/* set block-size for cbom and/or cboz extension if available */  in riscv_init_cbo_blocksizes()
135 			cbo_get_block_size(node, "riscv,cbom-block-size",  in riscv_init_cbo_blocksizes()
137 			cbo_get_block_size(node, "riscv,cboz-block-size",  in riscv_init_cbo_blocksizes()