Lines Matching +full:isa +full:- +full:base
1 // SPDX-License-Identifier: GPL-2.0-only
30 #include "copy-unaligned.h"
32 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
37 #define MISALIGNED_COPY_SIZE ((MISALIGNED_BUFFER_SIZE / 2) - 0x80)
41 /* Host ISA bitmap */
44 /* Per-cpu ISA extensions. */
53 * riscv_isa_extension_base() - Get base extension word
55 * @isa_bitmap: ISA bitmap to use
56 * Return: base extension word as unsigned long value
58 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
69 * __riscv_isa_extension_available() - Check whether given extension
72 * @isa_bitmap: ISA bitmap to use
76 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
94 pr_err("Zicbom detected in ISA string, disabling as no cbom-block-size found\n"); in riscv_isa_extension_check()
97 pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n"); in riscv_isa_extension_check()
103 pr_err("Zicboz detected in ISA string, disabling as no cboz-block-size found\n"); in riscv_isa_extension_check()
106 pr_err("Zicboz disabled as cboz-block-size present, but is not a power-of-2\n"); in riscv_isa_extension_check()
206 * While the [ms]envcfg CSRs were not defined until version 1.12 of the RISC-V
207 * privileged ISA, the existence of the CSRs is implied by any extension which
208 * specifies [ms]envcfg bit(s). Hence, we define a custom ISA extension for the
216 * The canonical order of ISA extension names in the ISA string is defined in
219 * Ordinarily, for in-kernel data structures, this order is unimportant but
220 * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo.
225 * 1. All multi-letter extensions must be separated from other extensions by an
229 * single-letter extensions and before any higher-privileged extensions.
236 * 3. Standard supervisor-level extensions (starting with 'S') must be listed
237 * after standard unprivileged extensions. If multiple supervisor-level
240 * 4. Standard machine-level extensions (starting with 'Zxm') must be listed
241 * after any lower-privileged, standard extensions. If multiple
242 * machine-level extensions are listed, they must be ordered
245 * 5. Non-standard extensions (starting with 'X') must be listed after all
246 * standard extensions. If multiple non-standard extensions are listed, they
328 if ((name_end - name == strlen(ext->name)) && in match_isa_ext()
329 !strncasecmp(name, ext->name, name_end - name)) { in match_isa_ext()
331 * If this is a bundle, enable all the ISA extensions that in match_isa_ext()
334 if (ext->subset_ext_size) { in match_isa_ext()
335 for (int i = 0; i < ext->subset_ext_size; i++) { in match_isa_ext()
336 if (riscv_isa_extension_check(ext->subset_ext_ids[i])) in match_isa_ext()
337 set_bit(ext->subset_ext_ids[i], isainfo->isa); in match_isa_ext()
345 if (riscv_isa_extension_check(ext->id)) in match_isa_ext()
346 set_bit(ext->id, isainfo->isa); in match_isa_ext()
351 unsigned long *isa2hwcap, const char *isa) in riscv_parse_isa_string() argument
359 isa += 4; in riscv_parse_isa_string()
361 while (*isa) { in riscv_parse_isa_string()
362 const char *ext = isa++; in riscv_parse_isa_string()
363 const char *ext_end = isa; in riscv_parse_isa_string()
369 * Workaround for invalid single-letter 's' & 'u' (QEMU). in riscv_parse_isa_string()
371 * not valid ISA extensions. It works unless the first in riscv_parse_isa_string()
372 * multi-letter extension in the ISA string begins with in riscv_parse_isa_string()
375 if (ext[-1] != '_' && ext[1] == 'u') { in riscv_parse_isa_string()
376 ++isa; in riscv_parse_isa_string()
388 * As multi-letter extensions must be split from other multi-letter in riscv_parse_isa_string()
389 * extensions with an "_", the end of a multi-letter extension will in riscv_parse_isa_string()
391 * multi-letter extension. in riscv_parse_isa_string()
402 * A simple re-increment solves this problem. in riscv_parse_isa_string()
405 for (; *isa && *isa != '_'; ++isa) in riscv_parse_isa_string()
406 if (unlikely(!isalnum(*isa))) in riscv_parse_isa_string()
409 ext_end = isa; in riscv_parse_isa_string()
413 if (!isdigit(ext_end[-1])) in riscv_parse_isa_string()
416 while (isdigit(*--ext_end)) in riscv_parse_isa_string()
419 if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) { in riscv_parse_isa_string()
424 while (isdigit(*--ext_end)) in riscv_parse_isa_string()
431 * Things are a little easier for single-letter extensions, as they in riscv_parse_isa_string()
435 * ensure that, when isa was incremented at the start of the loop, in riscv_parse_isa_string()
438 * If we are already on a non-digit, there is nothing to do. Either in riscv_parse_isa_string()
439 * we have a multi-letter extension's _, or the start of an in riscv_parse_isa_string()
453 if (!isdigit(*isa)) in riscv_parse_isa_string()
456 while (isdigit(*++isa)) in riscv_parse_isa_string()
459 if (tolower(*isa) != 'p') in riscv_parse_isa_string()
462 if (!isdigit(*++isa)) { in riscv_parse_isa_string()
463 --isa; in riscv_parse_isa_string()
467 while (isdigit(*++isa)) in riscv_parse_isa_string()
474 * The parser expects that at the start of an iteration isa points to the in riscv_parse_isa_string()
476 * on meeting a non-alphanumeric character, an extra increment is needed in riscv_parse_isa_string()
477 * where the succeeding extension is a multi-letter prefixed with an "_". in riscv_parse_isa_string()
479 if (*isa == '_') in riscv_parse_isa_string()
480 ++isa; in riscv_parse_isa_string()
485 int nr = tolower(*ext) - 'a'; in riscv_parse_isa_string()
489 set_bit(nr, isainfo->isa); in riscv_parse_isa_string()
501 const char *isa; in riscv_fill_hwcap_from_isa_string() local
524 rc = of_property_read_string(node, "riscv,isa", &isa); in riscv_fill_hwcap_from_isa_string()
527 pr_warn("Unable to find \"riscv,isa\" devicetree entry\n"); in riscv_fill_hwcap_from_isa_string()
531 rc = acpi_get_riscv_isa(rhct, cpu, &isa); in riscv_fill_hwcap_from_isa_string()
533 pr_warn("Unable to get ISA for the hart - %d\n", cpu); in riscv_fill_hwcap_from_isa_string()
538 riscv_parse_isa_string(&this_hwcap, isainfo, isa2hwcap, isa); in riscv_fill_hwcap_from_isa_string()
541 * These ones were as they were part of the base ISA when the in riscv_fill_hwcap_from_isa_string()
542 * port & dt-bindings were upstreamed, and so can be set in riscv_fill_hwcap_from_isa_string()
543 * unconditionally where `i` is in riscv,isa on DT systems. in riscv_fill_hwcap_from_isa_string()
546 set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa); in riscv_fill_hwcap_from_isa_string()
547 set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa); in riscv_fill_hwcap_from_isa_string()
548 set_bit(RISCV_ISA_EXT_ZICNTR, isainfo->isa); in riscv_fill_hwcap_from_isa_string()
549 set_bit(RISCV_ISA_EXT_ZIHPM, isainfo->isa); in riscv_fill_hwcap_from_isa_string()
553 * "V" in ISA strings is ambiguous in practice: it should mean in riscv_fill_hwcap_from_isa_string()
554 * just the standard V-1.0 but vendors aren't well behaved. in riscv_fill_hwcap_from_isa_string()
555 * Many vendors with T-Head CPU cores which implement the 0.7.1 in riscv_fill_hwcap_from_isa_string()
557 * CPU cores with the ratified spec will contain non-zero in riscv_fill_hwcap_from_isa_string()
563 clear_bit(RISCV_ISA_EXT_v, isainfo->isa); in riscv_fill_hwcap_from_isa_string()
567 * All "okay" hart should have same isa. Set HWCAP based on in riscv_fill_hwcap_from_isa_string()
577 bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); in riscv_fill_hwcap_from_isa_string()
579 bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); in riscv_fill_hwcap_from_isa_string()
601 if (!of_property_present(cpu_node, "riscv,isa-extensions")) { in riscv_fill_hwcap_from_ext_list()
609 if (of_property_match_string(cpu_node, "riscv,isa-extensions", in riscv_fill_hwcap_from_ext_list()
610 ext->property) < 0) in riscv_fill_hwcap_from_ext_list()
613 if (ext->subset_ext_size) { in riscv_fill_hwcap_from_ext_list()
614 for (int j = 0; j < ext->subset_ext_size; j++) { in riscv_fill_hwcap_from_ext_list()
615 if (riscv_isa_extension_check(ext->subset_ext_ids[i])) in riscv_fill_hwcap_from_ext_list()
616 set_bit(ext->subset_ext_ids[j], isainfo->isa); in riscv_fill_hwcap_from_ext_list()
620 if (riscv_isa_extension_check(ext->id)) { in riscv_fill_hwcap_from_ext_list()
621 set_bit(ext->id, isainfo->isa); in riscv_fill_hwcap_from_ext_list()
632 * All "okay" harts should have same isa. Set HWCAP based on in riscv_fill_hwcap_from_ext_list()
641 bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); in riscv_fill_hwcap_from_ext_list()
643 bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX); in riscv_fill_hwcap_from_ext_list()
647 return -ENOENT; in riscv_fill_hwcap_from_ext_list()
670 isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; in riscv_fill_hwcap()
671 isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; in riscv_fill_hwcap()
672 isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A; in riscv_fill_hwcap()
673 isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F; in riscv_fill_hwcap()
674 isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D; in riscv_fill_hwcap()
675 isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C; in riscv_fill_hwcap()
676 isa2hwcap['v' - 'a'] = COMPAT_HWCAP_ISA_V; in riscv_fill_hwcap()
684 pr_info("Falling back to deprecated \"riscv,isa\"\n"); in riscv_fill_hwcap()
701 * ISA string in device tree might have 'v' flag, but in riscv_fill_hwcap()
713 pr_info("riscv: base ISA extensions %s\n", print_str); in riscv_fill_hwcap()
726 hwcap = (elf_hwcap & ((1UL << RISCV_ISA_EXT_BASE) - 1)); in riscv_get_elf_hwcap()
755 word_cycles = -1ULL; in check_unaligned_access()
775 if ((end_cycles - start_cycles) < word_cycles) in check_unaligned_access()
776 word_cycles = end_cycles - start_cycles; in check_unaligned_access()
779 byte_cycles = -1ULL; in check_unaligned_access()
791 if ((end_cycles - start_cycles) < byte_cycles) in check_unaligned_access()
792 byte_cycles = end_cycles - start_cycles; in check_unaligned_access()
862 modify_unaligned_access_branches(&fast_except_me, num_online_cpus() - 1); in set_unaligned_access_static_branches_except_cpu()
905 return -ENOMEM; in riscv_online_cpu()
985 * 16-bit vendor ID and a 32-bit patch ID. A non-zero vendor ID means the
986 * patch site is for an erratum, identified by the 32-bit patch ID. When
988 * further break down patch ID into two 16-bit numbers. The lower 16 bits
992 * patching on a per-site basis will provide non-zero values and implement
1027 if (alt->vendor_id != 0) in riscv_cpufeature_patch_func()
1030 id = PATCH_ID_CPUFEATURE_ID(alt->patch_id); in riscv_cpufeature_patch_func()
1033 WARN(1, "This extension id:%d is not in ISA extension list", id); in riscv_cpufeature_patch_func()
1040 value = PATCH_ID_CPUFEATURE_VALUE(alt->patch_id); in riscv_cpufeature_patch_func()
1048 patch_text_nosync(oldptr, altptr, alt->alt_len); in riscv_cpufeature_patch_func()
1049 riscv_alternative_fix_offsets(oldptr, alt->alt_len, oldptr - altptr); in riscv_cpufeature_patch_func()