Lines Matching +full:0 +full:- +full:3
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/interrupt-controller/irq.h>
9 #include "sg2042-cpus.dtsi"
13 #address-cells = <2>;
14 #size-cells = <2>;
15 dma-noncoherent;
22 compatible = "simple-bus";
23 #address-cells = <2>;
24 #size-cells = <2>;
27 clint_mswi: interrupt-controller@7094000000 {
28 compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
29 reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
30 interrupts-extended = <&cpu0_intc 3>,
31 <&cpu1_intc 3>,
32 <&cpu2_intc 3>,
33 <&cpu3_intc 3>,
34 <&cpu4_intc 3>,
35 <&cpu5_intc 3>,
36 <&cpu6_intc 3>,
37 <&cpu7_intc 3>,
38 <&cpu8_intc 3>,
39 <&cpu9_intc 3>,
40 <&cpu10_intc 3>,
41 <&cpu11_intc 3>,
42 <&cpu12_intc 3>,
43 <&cpu13_intc 3>,
44 <&cpu14_intc 3>,
45 <&cpu15_intc 3>,
46 <&cpu16_intc 3>,
47 <&cpu17_intc 3>,
48 <&cpu18_intc 3>,
49 <&cpu19_intc 3>,
50 <&cpu20_intc 3>,
51 <&cpu21_intc 3>,
52 <&cpu22_intc 3>,
53 <&cpu23_intc 3>,
54 <&cpu24_intc 3>,
55 <&cpu25_intc 3>,
56 <&cpu26_intc 3>,
57 <&cpu27_intc 3>,
58 <&cpu28_intc 3>,
59 <&cpu29_intc 3>,
60 <&cpu30_intc 3>,
61 <&cpu31_intc 3>,
62 <&cpu32_intc 3>,
63 <&cpu33_intc 3>,
64 <&cpu34_intc 3>,
65 <&cpu35_intc 3>,
66 <&cpu36_intc 3>,
67 <&cpu37_intc 3>,
68 <&cpu38_intc 3>,
69 <&cpu39_intc 3>,
70 <&cpu40_intc 3>,
71 <&cpu41_intc 3>,
72 <&cpu42_intc 3>,
73 <&cpu43_intc 3>,
74 <&cpu44_intc 3>,
75 <&cpu45_intc 3>,
76 <&cpu46_intc 3>,
77 <&cpu47_intc 3>,
78 <&cpu48_intc 3>,
79 <&cpu49_intc 3>,
80 <&cpu50_intc 3>,
81 <&cpu51_intc 3>,
82 <&cpu52_intc 3>,
83 <&cpu53_intc 3>,
84 <&cpu54_intc 3>,
85 <&cpu55_intc 3>,
86 <&cpu56_intc 3>,
87 <&cpu57_intc 3>,
88 <&cpu58_intc 3>,
89 <&cpu59_intc 3>,
90 <&cpu60_intc 3>,
91 <&cpu61_intc 3>,
92 <&cpu62_intc 3>,
93 <&cpu63_intc 3>;
97 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
98 reg = <0x00000070 0xac004000 0x00000000 0x0000c000>;
99 reg-names = "mtimecmp";
100 interrupts-extended = <&cpu0_intc 7>,
107 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
108 reg = <0x00000070 0xac014000 0x00000000 0x0000c000>;
109 reg-names = "mtimecmp";
110 interrupts-extended = <&cpu4_intc 7>,
117 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
118 reg = <0x00000070 0xac024000 0x00000000 0x0000c000>;
119 reg-names = "mtimecmp";
120 interrupts-extended = <&cpu8_intc 7>,
127 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
128 reg = <0x00000070 0xac034000 0x00000000 0x0000c000>;
129 reg-names = "mtimecmp";
130 interrupts-extended = <&cpu12_intc 7>,
137 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
138 reg = <0x00000070 0xac044000 0x00000000 0x0000c000>;
139 reg-names = "mtimecmp";
140 interrupts-extended = <&cpu16_intc 7>,
147 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
148 reg = <0x00000070 0xac054000 0x00000000 0x0000c000>;
149 reg-names = "mtimecmp";
150 interrupts-extended = <&cpu20_intc 7>,
157 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
158 reg = <0x00000070 0xac064000 0x00000000 0x0000c000>;
159 reg-names = "mtimecmp";
160 interrupts-extended = <&cpu24_intc 7>,
167 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
168 reg = <0x00000070 0xac074000 0x00000000 0x0000c000>;
169 reg-names = "mtimecmp";
170 interrupts-extended = <&cpu28_intc 7>,
177 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
178 reg = <0x00000070 0xac084000 0x00000000 0x0000c000>;
179 reg-names = "mtimecmp";
180 interrupts-extended = <&cpu32_intc 7>,
187 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
188 reg = <0x00000070 0xac094000 0x00000000 0x0000c000>;
189 reg-names = "mtimecmp";
190 interrupts-extended = <&cpu36_intc 7>,
197 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
198 reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>;
199 reg-names = "mtimecmp";
200 interrupts-extended = <&cpu40_intc 7>,
207 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
208 reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>;
209 reg-names = "mtimecmp";
210 interrupts-extended = <&cpu44_intc 7>,
217 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
218 reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>;
219 reg-names = "mtimecmp";
220 interrupts-extended = <&cpu48_intc 7>,
227 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
228 reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>;
229 reg-names = "mtimecmp";
230 interrupts-extended = <&cpu52_intc 7>,
237 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
238 reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>;
239 reg-names = "mtimecmp";
240 interrupts-extended = <&cpu56_intc 7>,
247 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
248 reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>;
249 reg-names = "mtimecmp";
250 interrupts-extended = <&cpu60_intc 7>,
256 intc: interrupt-controller@7090000000 {
257 compatible = "sophgo,sg2042-plic", "thead,c900-plic";
258 #address-cells = <0>;
259 #interrupt-cells = <2>;
260 reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
261 interrupt-controller;
262 interrupts-extended =
331 compatible = "snps,dw-apb-uart";
332 reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
333 interrupt-parent = <&intc>;
335 clock-frequency = <500000000>;
336 reg-shift = <2>;
337 reg-io-width = <4>;