dts/sophgo/cv18xx.dtsi

1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
10 	#address-cells = <1>;
11 	#size-cells = <1>;
14 		#address-cells = <1>;
15 		#size-cells = <0>;
16 		timebase-frequency = <25000000>;
21 			reg = <0>;
22 			d-cache-block-size = <64>;
23 			d-cache-sets = <512>;
24 			d-cache-size = <65536>;
25 			i-cache-block-size = <64>;
26 			i-cache-sets = <128>;
27 			i-cache-size = <32768>;
28 			mmu-type = "riscv,sv39";
30 			riscv,isa-base = "rv64i";
31 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
34 			cpu0_intc: interrupt-controller {
35 				compatible = "riscv,cpu-intc";
36 				interrupt-controller;
37 				#interrupt-cells = <1>;
43 		compatible = "fixed-clock";
44 		clock-output-names = "osc_25m";
45 		#clock-cells = <0>;
49 		compatible = "simple-bus";
50 		interrupt-parent = <&plic>;
51 		#address-cells = <1>;
52 		#size-cells = <1>;
53 		dma-noncoherent;
57 			compatible = "snps,dw-apb-gpio";
58 			reg = <0x3020000 0x1000>;
59 			#address-cells = <1>;
60 			#size-cells = <0>;
62 			porta: gpio-controller@0 {
63 				compatible = "snps,dw-apb-gpio-port";
64 				gpio-controller;
65 				#gpio-cells = <2>;
67 				reg = <0>;
68 				interrupt-controller;
69 				#interrupt-cells = <2>;
75 			compatible = "snps,dw-apb-gpio";
76 			reg = <0x3021000 0x1000>;
77 			#address-cells = <1>;
78 			#size-cells = <0>;
80 			portb: gpio-controller@0 {
81 				compatible = "snps,dw-apb-gpio-port";
82 				gpio-controller;
83 				#gpio-cells = <2>;
85 				reg = <0>;
86 				interrupt-controller;
87 				#interrupt-cells = <2>;
93 			compatible = "snps,dw-apb-gpio";
94 			reg = <0x3022000 0x1000>;
95 			#address-cells = <1>;
96 			#size-cells = <0>;
98 			portc: gpio-controller@0 {
99 				compatible = "snps,dw-apb-gpio-port";
100 				gpio-controller;
101 				#gpio-cells = <2>;
103 				reg = <0>;
104 				interrupt-controller;
105 				#interrupt-cells = <2>;
111 			compatible = "snps,dw-apb-gpio";
112 			reg = <0x3023000 0x1000>;
113 			#address-cells = <1>;
114 			#size-cells = <0>;
116 			portd: gpio-controller@0 {
117 				compatible = "snps,dw-apb-gpio-port";
118 				gpio-controller;
119 				#gpio-cells = <2>;
121 				reg = <0>;
122 				interrupt-controller;
123 				#interrupt-cells = <2>;
129 			compatible = "snps,dw-apb-uart";
130 			reg = <0x04140000 0x100>;
133 			reg-shift = <2>;
134 			reg-io-width = <4>;
139 			compatible = "snps,dw-apb-uart";
140 			reg = <0x04150000 0x100>;
143 			reg-shift = <2>;
144 			reg-io-width = <4>;
149 			compatible = "snps,dw-apb-uart";
150 			reg = <0x04160000 0x100>;
153 			reg-shift = <2>;
154 			reg-io-width = <4>;
159 			compatible = "snps,dw-apb-uart";
160 			reg = <0x04170000 0x100>;
163 			reg-shift = <2>;
164 			reg-io-width = <4>;
169 			compatible = "snps,dw-apb-uart";
170 			reg = <0x041c0000 0x100>;
173 			reg-shift = <2>;
174 			reg-io-width = <4>;
178 		plic: interrupt-controller@70000000 {
179 			reg = <0x70000000 0x4000000>;
180 			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
181 			interrupt-controller;
182 			#address-cells = <0>;
183 			#interrupt-cells = <2>;
188 			reg = <0x74000000 0x10000>;
189 			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;