dts/microchip/mpfs-icicle-kit.dts

1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
7 #include "mpfs-icicle-kit-fabric.dtsi"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h>
12 	model = "Microchip PolarFire-SoC Icicle Kit";
13 	compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
26 		stdout-path = "serial1:115200n8";
30 		compatible = "gpio-leds";
32 		led-1 {
38 		led-2 {
44 		led-3 {
50 		led-4 {
69 	reserved-memory {
70 		#address-cells = <2>;
71 		#size-cells = <2>;
76 			no-map;
110 	phy-mode = "sgmii";
111 	phy-handle = <&phy0>;
116 	phy-mode = "sgmii";
117 	phy-handle = <&phy1>;
120 	phy1: ethernet-phy@9 {
124 	phy0: ethernet-phy@8 {
133 &mmc {
134 	bus-width = <4>;
135 	disable-wp;
136 	cap-sd-highspeed;
137 	cap-mmc-highspeed;
138 	mmc-ddr-1_8v;
139 	mmc-hs200-1_8v;
140 	sd-uhs-sdr12;
141 	sd-uhs-sdr25;
142 	sd-uhs-sdr50;
143 	sd-uhs-sdr104;
172 	clock-frequency = <125000000>;
176 	clock-frequency = <50000000>;
198 	 * silicon (write?) access to this flash to non-functional. The system
201 	 * it to the flash instead should work though. Pre-production or later
206 	sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT
207 		compatible = "jedec,spi-nor";
208 		#address-cells = <1>;
209 		#size-cells = <1>;
210 		spi-max-frequency = <20000000>;
211 		spi-rx-bus-width = <1>;