Lines Matching +full:- +full:- +full:print +full:- +full:architecture

1 /* ppc.h -- Header file for PowerPC opcode table
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
73 /* Opcode is defined for the PowerPC architecture. */
76 /* Opcode is defined for the POWER (RS/6000) architecture. */
79 /* Opcode is defined for the POWER2 (Rios 2) architecture. */
88 (ie, compiler's -mcpu=common or assembler's -mcom). More than just
95 for the assembler's -many option, and it eliminates duplicates). */
101 /* Opcode is supported as part of the 64-bit bridge. */
116 /* Opcode is only supported by Power4 architecture. */
119 /* Opcode is only supported by Power7 architecture. */
143 /* Opcode is only supported by Power5 architecture. */
149 /* Opcode is only supported by Power6 architecture. */
164 /* Opcode is supported by Vector-Scalar (VSX) Unit */
191 /* Opcode is only supported by Power8 architecture. */
208 /* Opcode is only supported by Power9 architecture. */
211 /* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08. */
220 /* A macro to determine if the instruction is a 2-byte VLE insn. */
239 is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate
248 if (o->shift >= 0)
249 i |= (op & o->bitm) << o->shift;
251 i |= (op & o->bitm) >> -o->shift;
269 if (o->shift >= 0)
270 op = (i >> o->shift) & o->bitm;
272 op = (i << -o->shift) & o->bitm;
273 if ((o->flags & PPC_OPERAND_SIGNED) != 0)
281 non-zero if this operand type can not actually be extracted from
299 #define PPC_OPSHIFT_INV (-1U << 31)
308 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
336 /* This operand names a register. The disassembler uses this to print
340 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
360 print this operand out only if it is not zero. */
367 either 4 or 5 operands. The disassembler should print this operand
388 /* Valid range of operand is 0..n rather than 0..n-1. */
396 /* This operand names a vector-scalar unit register. The disassembler
409 only optional when generating 32-bit code. */
441 if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0) in ppc_optional_operand_value()
442 return (operand+1)->shift; in ppc_optional_operand_value()