27 	{ .compatible = "fsl,mpc5200-xlb", },
28 	{ .compatible = "mpc5200-xlb", },
32 	{ .compatible = "fsl,mpc5200-immr", },
33 	{ .compatible = "fsl,mpc5200b-immr", },
34 	{ .compatible = "simple-bus", },
73 	out_be32(&xlb->master_pri_enable, 0xff);  in mpc5200_setup_xlb_arbiter()
74 	out_be32(&xlb->master_priority, 0x11111111);  in mpc5200_setup_xlb_arbiter()
79 	 *  transaction and re-enable it afterwards ...)  in mpc5200_setup_xlb_arbiter()
83 		out_be32(&xlb->config, in_be32(&xlb->config) | MPC52xx_XLB_CFG_PLDIS);  in mpc5200_setup_xlb_arbiter()
112 	{ .compatible = "fsl,mpc5200-gpt", },
113 	{ .compatible = "mpc5200-gpt", }, /* old */
117 	{ .compatible = "fsl,mpc5200-cdm", },
118 	{ .compatible = "mpc5200-cdm", }, /* old */
122 	{ .compatible = "fsl,mpc5200-gpio", },
126 	{ .compatible = "fsl,mpc5200-gpio-wkup", },
141 	 * on a gpt0, so check has-wdt property before mapping.  in mpc52xx_map_common_devices()
144 		if (of_property_read_bool(np, "fsl,has-wdt") ||  in mpc52xx_map_common_devices()
145 		    of_property_read_bool(np, "has-wdt")) {  in mpc52xx_map_common_devices()
169  * mpc52xx_set_psc_clkdiv: Set clock divider in the CDM for PSC ports
172  * @clkdiv: clock divider value to put into CDM PSC register.
183 		return -ENODEV;  in mpc52xx_set_psc_clkdiv()
187 	case 1: reg = &mpc52xx_cdm->mclken_div_psc1; mask = 0x20; break;  in mpc52xx_set_psc_clkdiv()
188 	case 2: reg = &mpc52xx_cdm->mclken_div_psc2; mask = 0x40; break;  in mpc52xx_set_psc_clkdiv()
189 	case 3: reg = &mpc52xx_cdm->mclken_div_psc3; mask = 0x80; break;  in mpc52xx_set_psc_clkdiv()
190 	case 6: reg = &mpc52xx_cdm->mclken_div_psc6; mask = 0x10; break;  in mpc52xx_set_psc_clkdiv()
192 		return -ENODEV;  in mpc52xx_set_psc_clkdiv()
195 	/* Set the rate and enable the clock */  in mpc52xx_set_psc_clkdiv()
198 	val = in_be32(&mpc52xx_cdm->clk_enables);  in mpc52xx_set_psc_clkdiv()
199 	out_be32(&mpc52xx_cdm->clk_enables, val | mask);  in mpc52xx_set_psc_clkdiv()
207  * mpc52xx_restart: ppc_md->restart hook for mpc5200 using the watchdog timer
216 		out_be32(&mpc52xx_wdt->mode, 0x00000000);  in mpc52xx_restart()
217 		out_be32(&mpc52xx_wdt->count, 0x000000ff);  in mpc52xx_restart()
218 		out_be32(&mpc52xx_wdt->mode, 0x00009004);  in mpc52xx_restart()
251 		return -ENODEV;  in mpc5200_psc_ac97_gpio_reset()
268 		       "cold-reset will be performed\n");  in mpc5200_psc_ac97_gpio_reset()
269 		return -ENODEV;  in mpc5200_psc_ac97_gpio_reset()
274 	/* Reconfigure pin-muxing to gpio */  in mpc5200_psc_ac97_gpio_reset()
275 	mux = in_be32(&simple_gpio->port_config);  in mpc5200_psc_ac97_gpio_reset()
276 	out_be32(&simple_gpio->port_config, mux & (~gpio));  in mpc5200_psc_ac97_gpio_reset()
278 	/* enable gpio pins for output */  in mpc5200_psc_ac97_gpio_reset()
279 	setbits8(&wkup_gpio->wkup_gpioe, reset);  in mpc5200_psc_ac97_gpio_reset()
280 	setbits32(&simple_gpio->simple_gpioe, sync | out);  in mpc5200_psc_ac97_gpio_reset()
282 	setbits8(&wkup_gpio->wkup_ddr, reset);  in mpc5200_psc_ac97_gpio_reset()
283 	setbits32(&simple_gpio->simple_ddr, sync | out);  in mpc5200_psc_ac97_gpio_reset()
286 	clrbits32(&simple_gpio->simple_dvo, sync | out);  in mpc5200_psc_ac97_gpio_reset()
287 	clrbits8(&wkup_gpio->wkup_dvo, reset);  in mpc5200_psc_ac97_gpio_reset()
293 	setbits8(&wkup_gpio->wkup_dvo, reset);  in mpc5200_psc_ac97_gpio_reset()
299 	/* Restore pin-muxing */  in mpc5200_psc_ac97_gpio_reset()
300 	out_be32(&simple_gpio->port_config, mux);  in mpc5200_psc_ac97_gpio_reset()