1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include "isa207-common.h"
11 PMU_FORMAT_ATTR(event,		"config:0-49");
12 PMU_FORMAT_ATTR(pmcxsel,	"config:0-7");
15 PMU_FORMAT_ATTR(unit,		"config:12-15");
16 PMU_FORMAT_ATTR(pmc,		"config:16-19");
17 PMU_FORMAT_ATTR(cache_sel,	"config:20-23");
18 PMU_FORMAT_ATTR(sample_mode,	"config:24-28");
19 PMU_FORMAT_ATTR(thresh_sel,	"config:29-31");
20 PMU_FORMAT_ATTR(thresh_stop,	"config:32-35");
21 PMU_FORMAT_ATTR(thresh_start,	"config:36-39");
22 PMU_FORMAT_ATTR(thresh_cmp,	"config:40-49");
90 	 * mode and will be un-changed when setting MMCRA[63] (Marked events).  in mmcra_sdar_mode()
98 	 *      requires that we set a non-zero value.  in mmcra_sdar_mode()
131 		while ((64 - __builtin_clzl(value)) > 8) {  in p10_thresh_cmp_val()
142 			result = -1;  in p10_thresh_cmp_val()
238 				ret |= P(LVL, HIT) | LEVEL(PMEM);  in isa207_find_source()
242 				ret |= P(LVL, HIT) | LEVEL(PMEM) | REM;  in isa207_find_source()
318 		dsrc->val = 0;  in isa207_get_mem_data_src()
330 	dsrc->val = isa207_find_source(idx, sub_idx);  in isa207_get_mem_data_src()
347 			dsrc->val |= P(OP, LOAD);  in isa207_get_mem_data_src()
350 			dsrc->val |= P(OP, STORE);  in isa207_get_mem_data_src()
353 			dsrc->val |= P(OP, NA);  in isa207_get_mem_data_src()
357 		dsrc->val |= (val == 1) ? P(OP, LOAD) : P(OP, STORE);  in isa207_get_mem_data_src()
384 	 * - store memory latency in the lower 32 bits.  in isa207_get_mem_weight()
385 	 * - For ISA v3.1, use remaining two 16 bit fields of  in isa207_get_mem_weight()
391 		weight_fields->full = weight_lat;  in isa207_get_mem_weight()
393 		weight_fields->var1_dw = (u32)weight_lat;  in isa207_get_mem_weight()
395 			weight_fields->var2_w = P10_SIER2_FINISH_CYC(mfspr(SPRN_SIER2));  in isa207_get_mem_weight()
396 			weight_fields->var3_w = P10_SIER2_DISPATCH_CYC(mfspr(SPRN_SIER2));  in isa207_get_mem_weight()
409 		return -1;  in isa207_get_constraint()
425 			return -1;  in isa207_get_constraint()
432 			return -1;  in isa207_get_constraint()
439 		 * they do not support most of the constraint bits. Add a check  in isa207_get_constraint()
449 		 * Add to number of counters in use. Note this includes events with  in isa207_get_constraint()
450 		 * a PMC of 0 - they still need a PMC, it's just assigned later.  in isa207_get_constraint()
481 			return -1;  in isa207_get_constraint()
506 			return -1;  in isa207_get_constraint()
512 			return -1;  in isa207_get_constraint()
523 				return -1;  in isa207_get_constraint()
533 		return -1;  in isa207_get_constraint()
538 			return -1;  in isa207_get_constraint()
654 				val = (pevents[i]->attr.config1 >> p10_EVENT_THR_CMP_SHIFT) &  in isa207_compute_mmcr()
676 		if (pevents[i]->attr.exclude_user)  in isa207_compute_mmcr()
679 		if (pevents[i]->attr.exclude_hv)  in isa207_compute_mmcr()
682 		if (pevents[i]->attr.exclude_kernel) {  in isa207_compute_mmcr()
689 		if (pevents[i]->attr.exclude_idle)  in isa207_compute_mmcr()
700 		hwc[i] = pmc - 1;  in isa207_compute_mmcr()
704 	mmcr->mmcr0 = 0;  in isa207_compute_mmcr()
706 	/* pmc_inuse is 1-based */  in isa207_compute_mmcr()
708 		mmcr->mmcr0 = MMCR0_PMC1CE;  in isa207_compute_mmcr()
711 		mmcr->mmcr0 |= MMCR0_PMCjCE;  in isa207_compute_mmcr()
715 		mmcr->mmcr0 |= MMCR0_FC56;  in isa207_compute_mmcr()
723 		mmcr->mmcr0 |= MMCR0_PMCCEXT;  in isa207_compute_mmcr()
725 	mmcr->mmcr1 = mmcr1;  in isa207_compute_mmcr()
726 	mmcr->mmcra = mmcra;  in isa207_compute_mmcr()
727 	mmcr->mmcr2 = mmcr2;  in isa207_compute_mmcr()
728 	mmcr->mmcr3 = mmcr3;  in isa207_compute_mmcr()
736 		mmcr->mmcr1 &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1));  in isa207_disable_pmc()
752 	return -1;  in find_alternative()
803 	u64 event = ev->attr.config;  in isa3XX_check_attr_config()
813 		return -EINVAL;  in isa3XX_check_attr_config()
827 		return -EINVAL;  in isa3XX_check_attr_config()
837 		return -EINVAL;  in isa3XX_check_attr_config()