Lines Matching +full:1 +full:v8

11 /* 0 == don't use VMX, 1 == use VMX */
98 	bf	cr7*4+3,1f
100 	addi	r4,r4,1
102 	addi	r3,r3,1
104 1:	bf	cr7*4+2,2f
110 2:	bf	cr7*4+1,3f
192 6:	bf	cr7*4+1,7f
247 12:	bf	cr7*4+1,13f
286 	 * 1 for the store side.
290 	ori	r9,r9,1		/* stream=1 */
294 	ble	1f
296 1:	lis	r0,0x0E00	/* depth=7 */
299 	ori	r10,r7,1	/* stream=1 */
301 	lis	r8,0x8000	/* GO=1 */
307 	/* setup write stream 1 */
328 	bf	cr7*4+3,1f
330 	addi	r4,r4,1
332 	addi	r3,r3,1
334 1:	bf	cr7*4+2,2f
340 2:	bf	cr7*4+1,3f
378 6:	bf	cr7*4+1,7f
439 	bf	cr7*4+1,9f
474 12:	bf	cr7*4+1,13f
499 	bf	cr7*4+3,1f
501 	addi	r4,r4,1
503 	addi	r3,r3,1
505 1:	bf	cr7*4+2,2f
511 2:	bf	cr7*4+1,3f
543 	VPERM(v8,v0,v1,v16)
545 err3;	stvx	v8,0,r3
551 	VPERM(v8,v0,v1,v16)
555 err3;	stvx	v8,0,r3
559 6:	bf	cr7*4+1,7f
561 	VPERM(v8,v0,v3,v16)
569 err3;	stvx	v8,0,r3
596 	VPERM(v8,v0,v7,v16)
612 err4;	stvx	v8,0,r3
632 	bf	cr7*4+1,9f
634 	VPERM(v8,v0,v3,v16)
642 err3;	stvx	v8,0,r3
650 	VPERM(v8,v0,v1,v16)
654 err3;	stvx	v8,0,r3
660 	VPERM(v8,v0,v1,v16)
662 err3;	stvx	v8,0,r3
677 12:	bf	cr7*4+1,13f