Lines Matching +full:3 +full:- +full:7
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
16 # 3. a += b; d ^= a; d <<<= 8;
17 # 4. c += d; b ^= c; b <<<= 7
22 # row3 = (row3 + row4), row2 = row3 xor row2, row2 rotate each word by 7
43 #include <asm/asm-offsets.h>
44 #include <asm/asm-compat.h>
81 stdu 1,-752(1)
201 vadduwm 3, 3, 7
210 vpermxor 15, 15, 3, 25
227 vxor 7, 7, 11
238 vrlw 7, 7, 25
247 vadduwm 3, 3, 7
258 vpermxor 15, 15, 3, 25
277 vxor 7, 7, 11
285 vrlw 7, 7, 28
297 vadduwm 2, 2, 7
298 vadduwm 3, 3, 4
307 vpermxor 14, 14, 3, 25
324 vxor 7, 7, 8
335 vrlw 7, 7, 25
345 vadduwm 2, 2, 7
346 vadduwm 3, 3, 4
357 vpermxor 14, 14, 3, 25
377 vxor 7, 7, 8
385 vrlw 7, 7, 28
399 vadduwm 3, 3, 7
403 vpermxor 15, 15, 3, 20
411 vxor 7, 7, 11
415 vrlw 7, 7, 21
419 vadduwm 3, 3, 7
423 vpermxor 15, 15, 3, 22
431 vxor 7, 7, 11
435 vrlw 7, 7, 23
440 vadduwm 2, 2, 7
441 vadduwm 3, 3, 4
445 vpermxor 14, 14, 3, 20
452 vxor 7, 7, 8
456 vrlw 7, 7, 21
460 vadduwm 2, 2, 7
461 vadduwm 3, 3, 4
465 vpermxor 14, 14, 3, 22
472 vxor 7, 7, 8
476 vrlw 7, 7, 23
487 xxpermdi 32+\a1, 10, 11, 3 # b0, b1, b2, b3
489 xxpermdi 32+\a3, 12, 13, 3 # d0, d1, d2, d3
494 vadduwm \S+0, \S+0, 16-\S
495 vadduwm \S+4, \S+4, 17-\S
496 vadduwm \S+8, \S+8, 18-\S
497 vadduwm \S+12, \S+12, 19-\S
499 vadduwm \S+1, \S+1, 16-\S
500 vadduwm \S+5, \S+5, 17-\S
501 vadduwm \S+9, \S+9, 18-\S
502 vadduwm \S+13, \S+13, 19-\S
504 vadduwm \S+2, \S+2, 16-\S
505 vadduwm \S+6, \S+6, 17-\S
506 vadduwm \S+10, \S+10, 18-\S
507 vadduwm \S+14, \S+14, 19-\S
509 vadduwm \S+3, \S+3, 16-\S
510 vadduwm \S+7, \S+7, 17-\S
511 vadduwm \S+11, \S+11, 18-\S
512 vadduwm \S+15, \S+15, 19-\S
524 lxvw4x 3, 19, 9
528 lxvw4x 7, 23, 9
541 xxlxor \S+44, \S+44, 3
545 xxlxor \S+45, \S+45, 7
587 # r17 - r31 mainly for Write_256 macro.
607 lxvw4x 48, 0, 3 # vr16, constants
608 lxvw4x 49, 17, 3 # vr17, key 1
609 lxvw4x 50, 18, 3 # vr18, key 2
610 lxvw4x 51, 19, 3 # vr19, counter, nonce
612 # create (0, 1, 2, 3) counters
616 vspltisw 3, 3
618 vmrglw 5, 2, 3
619 vsldoi 30, 4, 5, 8 # vr30 counter, 4 (0, 1, 2, 3)
622 vspltisw 23, 7
629 sradi 8, 7, 1
645 vadduwm 31, 30, 25 # counter = (0, 1, 2, 3) + (4, 4, 4, 4)
661 xxspltw 32+3, 16, 3
666 xxspltw 32+7, 17, 3
670 xxspltw 32+11, 18, 3
674 xxspltw 32+15, 19, 3
680 xxspltw 32+19, 16, 3
685 xxspltw 32+23, 17, 3
689 xxspltw 32+27, 18, 3
694 xxspltw 32+31, 19, 3
706 TP_4x 0, 1, 2, 3
707 TP_4x 4, 5, 6, 7
714 xxlor 3, 51, 51
723 xxlor 51, 3, 3
726 addi 15, 15, -256 # len -=256
732 TP_4x 16+0, 16+1, 16+2, 16+3
733 TP_4x 16+4, 16+5, 16+6, 16+7
744 addi 15, 15, -256 # len +=256
764 lxvw4x 48, 0, 3 # vr16, constants
765 lxvw4x 49, 17, 3 # vr17, key 1
766 lxvw4x 50, 18, 3 # vr18, key 2
767 lxvw4x 51, 19, 3 # vr19, counter, nonce
770 vspltisw 23, 7
776 sradi 8, 7, 1
783 vspltw 3, 16, 3
788 vspltw 7, 17, 3
792 vspltw 11, 18, 3
797 vspltw 15, 19, 3
806 TP_4x 0, 1, 2, 3
807 TP_4x 4, 5, 6, 7
814 addi 15, 15, -256 # len += 256
833 li 3, 0