boot/dts/xpedite5200.dts

1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
14 	#address-cells = <1>;
15 	#size-cells = <1>;
29 		#address-cells = <1>;
30 		#size-cells = <0>;
34 			reg = <0>;
35 			d-cache-line-size = <32>;	// 32 bytes
36 			i-cache-line-size = <32>;	// 32 bytes
37 			d-cache-size = <0x8000>;	// L1, 32K
38 			i-cache-size = <0x8000>;	// L1, 32K
39 			next-level-cache = <&L2>;
45 		reg = <0x0 0x0>;	// Filled in by U-Boot
49 		#address-cells = <1>;
50 		#size-cells = <1>;
53 		bus-frequency = <0>;
54 		compatible = "fsl,mpc8548-immr", "simple-bus";
56 		ecm-law@0 {
57 			compatible = "fsl,ecm-law";
58 			reg = <0x0 0x1000>;
59 			fsl,num-laws = <12>;
63 			compatible = "fsl,mpc8548-ecm", "fsl,ecm";
64 			reg = <0x1000 0x1000>;
66 			interrupt-parent = <&mpic>;
69 		memory-controller@2000 {
70 			compatible = "fsl,mpc8548-memory-controller";
71 			reg = <0x2000 0x1000>;
72 			interrupt-parent = <&mpic>;
76 		L2: l2-cache-controller@20000 {
77 			compatible = "fsl,mpc8548-l2-cache-controller";
78 			reg = <0x20000 0x1000>;
79 			cache-line-size = <32>;	// 32 bytes
80 			cache-size = <0x80000>;	// L2, 512K
81 			interrupt-parent = <&mpic>;
85 		/* On-card I2C */
87 			#address-cells = <1>;
88 			#size-cells = <0>;
89 			cell-index = <0>;
90 			compatible = "fsl-i2c";
91 			reg = <0x3000 0x100>;
93 			interrupt-parent = <&mpic>;
102 			 * 	4: Flash boot device indicator
109 				reg = <0x18>;
110 				#gpio-cells = <2>;
111 				gpio-controller;
118 				reg = <0x19>;
119 				#gpio-cells = <2>;
120 				gpio-controller;
126 				reg = <0x50>;
132 				reg = <0x68>;
137 				reg = <0x34>;
141 		/* Off-card I2C */
143 			#address-cells = <1>;
144 			#size-cells = <0>;
145 			cell-index = <1>;
146 			compatible = "fsl-i2c";
147 			reg = <0x3100 0x100>;
149 			interrupt-parent = <&mpic>;
154 			#address-cells = <1>;
155 			#size-cells = <1>;
156 			compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
157 			reg = <0x21300 0x4>;
159 			cell-index = <0>;
160 			dma-channel@0 {
161 				compatible = "fsl,mpc8548-dma-channel",
162 						"fsl,eloplus-dma-channel";
163 				reg = <0x0 0x80>;
164 				cell-index = <0>;
165 				interrupt-parent = <&mpic>;
168 			dma-channel@80 {
169 				compatible = "fsl,mpc8548-dma-channel",
170 						"fsl,eloplus-dma-channel";
171 				reg = <0x80 0x80>;
172 				cell-index = <1>;
173 				interrupt-parent = <&mpic>;
176 			dma-channel@100 {
177 				compatible = "fsl,mpc8548-dma-channel",
178 						"fsl,eloplus-dma-channel";
179 				reg = <0x100 0x80>;
180 				cell-index = <2>;
181 				interrupt-parent = <&mpic>;
184 			dma-channel@180 {
185 				compatible = "fsl,mpc8548-dma-channel",
186 						"fsl,eloplus-dma-channel";
187 				reg = <0x180 0x80>;
188 				cell-index = <3>;
189 				interrupt-parent = <&mpic>;
196 			#address-cells = <1>;
197 			#size-cells = <1>;
198 			cell-index = <0>;
202 			reg = <0x24000 0x1000>;
204 			local-mac-address = [ 00 00 00 00 00 00 ];
206 			interrupt-parent = <&mpic>;
207 			tbi-handle = <&tbi0>;
208 			phy-handle = <&phy0>;
211 				#address-cells = <1>;
212 				#size-cells = <0>;
213 				compatible = "fsl,gianfar-mdio";
214 				reg = <0x520 0x20>;
216 				phy0: ethernet-phy@1 {
217 					interrupt-parent = <&mpic>;
219 					reg = <0x1>;
221 				phy1: ethernet-phy@2 {
222 					interrupt-parent = <&mpic>;
224 					reg = <0x2>;
226 				phy2: ethernet-phy@3 {
227 					interrupt-parent = <&mpic>;
229 					reg = <0x3>;
231 				phy3: ethernet-phy@4 {
232 					interrupt-parent = <&mpic>;
234 					reg = <0x4>;
236 				tbi0: tbi-phy@11 {
237 					reg = <0x11>;
238 					device_type = "tbi-phy";
245 			#address-cells = <1>;
246 			#size-cells = <1>;
247 			cell-index = <1>;
251 			reg = <0x25000 0x1000>;
253 			local-mac-address = [ 00 00 00 00 00 00 ];
255 			interrupt-parent = <&mpic>;
256 			tbi-handle = <&tbi1>;
257 			phy-handle = <&phy1>;
260 				#address-cells = <1>;
261 				#size-cells = <0>;
262 				compatible = "fsl,gianfar-tbi";
263 				reg = <0x520 0x20>;
265 				tbi1: tbi-phy@11 {
266 					reg = <0x11>;
267 					device_type = "tbi-phy";
274 			#address-cells = <1>;
275 			#size-cells = <1>;
276 			cell-index = <2>;
280 			reg = <0x26000 0x1000>;
282 			local-mac-address = [ 00 00 00 00 00 00 ];
284 			interrupt-parent = <&mpic>;
285 			tbi-handle = <&tbi2>;
286 			phy-handle = <&phy2>;
289 				#address-cells = <1>;
290 				#size-cells = <0>;
291 				compatible = "fsl,gianfar-tbi";
292 				reg = <0x520 0x20>;
294 				tbi2: tbi-phy@11 {
295 					reg = <0x11>;
296 					device_type = "tbi-phy";
303 			#address-cells = <1>;
304 			#size-cells = <1>;
305 			cell-index = <3>;
309 			reg = <0x27000 0x1000>;
311 			local-mac-address = [ 00 00 00 00 00 00 ];
313 			interrupt-parent = <&mpic>;
314 			tbi-handle = <&tbi3>;
315 			phy-handle = <&phy3>;
318 				#address-cells = <1>;
319 				#size-cells = <0>;
320 				compatible = "fsl,gianfar-tbi";
321 				reg = <0x520 0x20>;
323 				tbi3: tbi-phy@11 {
324 					reg = <0x11>;
325 					device_type = "tbi-phy";
331 			cell-index = <0>;
334 			reg = <0x4500 0x100>;
335 			clock-frequency = <0>;
336 			current-speed = <115200>;
338 			interrupt-parent = <&mpic>;
342 			cell-index = <1>;
345 			reg = <0x4600 0x100>;
346 			clock-frequency = <0>;
347 			current-speed = <115200>;
349 			interrupt-parent = <&mpic>;
352 		global-utilities@e0000 {	// global utilities reg
353 			compatible = "fsl,mpc8548-guts";
354 			reg = <0xe0000 0x1000>;
355 			fsl,has-rstcr;
359 			interrupt-controller;
360 			#address-cells = <0>;
361 			#interrupt-cells = <2>;
362 			reg = <0x40000 0x40000>;
363 			compatible = "chrp,open-pic";
364 			device_type = "open-pic";
369 		compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
370 			     "simple-bus";
371 		#address-cells = <2>;
372 		#size-cells = <1>;
373 		reg = <0xef005000 0x100>;	// BRx, ORx, etc.
374 		interrupt-parent = <&mpic>;
378 			0 0x0 0xfc000000 0x04000000	// NOR boot flash
384 		nor-boot@0,0 {
385 			#address-cells = <1>;
386 			#size-cells = <1>;
387 			compatible = "cfi-flash";
388 			reg = <0 0x0 0x4000000>;
389 			bank-width = <2>;
393 				reg = <0x00000000 0x180000>;
396 				label = "Secondary OS";
397 				reg = <0x00180000 0x180000>;
401 				reg = <0x00300000 0x3c80000>;
404 				label = "Boot firmware";
405 				reg = <0x03f80000 0x80000>;
409 		nor-alternate@1,0 {
410 			#address-cells = <1>;
411 			#size-cells = <1>;
412 			compatible = "cfi-flash";
413 			reg = <1 0x0 0x4000000>;
414 			bank-width = <2>;
418 				reg = <0x00000000 0x3f80000>;
421 				label = "Alternate boot firmware";
422 				reg = <0x03f80000 0x80000>;
427 			#address-cells = <1>;
428 			#size-cells = <1>;
429 			compatible = "xes,address-ctl-nand";
430 			reg = <2 0x0 0x10000>;
431 			cle-line = <0x8>;	/* CLE tied to A3 */
432 			ale-line = <0x10>;	/* ALE tied to A4 */
434 			/* U-Boot should fix this up */
437 				reg = <0 0x40000000>;
444 		#interrupt-cells = <1>;
445 		#size-cells = <2>;
446 		#address-cells = <3>;
447 		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
449 		reg = <0xef008000 0x1000>;
450 		clock-frequency = <33333333>;
451 		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
452 		interrupt-map = <
457 		interrupt-parent = <&mpic>;
459 		bus-range = <0 0>;
464 	/* XMC PCIe is not yet enabled in U-Boot on XPedite5200 */