Lines Matching +full:0 +full:x00000700

23 #define CPR_PERD0_SPIDV_MASK   0x000F0000     /* SPI Clock Divider */
25 #define PLLC_SRC_MASK	       0x20000000     /* PLL feedback source */
27 #define PLLD_FBDV_MASK	       0x1F000000     /* PLL feedback divider value */
28 #define PLLD_FWDVA_MASK        0x000F0000     /* PLL forward divider A value */
29 #define PLLD_FWDVB_MASK        0x00000700     /* PLL forward divider B value */
31 #define PRIMAD_CPUDV_MASK      0x0F000000     /* CPU Clock Divisor Mask */
32 #define PRIMAD_PLBDV_MASK      0x000F0000     /* PLB Clock Divisor Mask */
33 #define PRIMAD_OPBDV_MASK      0x00000F00     /* OPB Clock Divisor Mask */
34 #define PRIMAD_EBCDV_MASK      0x0000000F     /* EBC Clock Divisor Mask */
36 #define PERD0_PWMDV_MASK       0xFF000000     /* PWM Divider Mask */
37 #define PERD0_SPIDV_MASK       0x000F0000     /* SPI Divider Mask */
38 #define PERD0_U0DV_MASK        0x0000FF00     /* UART 0 Divider Mask */
39 #define PERD0_U1DV_MASK        0x000000FF     /* UART 1 Divider Mask */
57 	sysclk = (in_8((unsigned char *)0x80000000) == 0xc) ? 66666666 : 33333000;  in get_clocks()
74 	if (pllFwdDivB == 0)  in get_clocks()
81 	if (pllFbkDiv == 0)  in get_clocks()
93 	if (pllPlbDiv == 0)  in get_clocks()
100 	if (pllExtBusDiv == 0)  in get_clocks()
107 	if (pllOpbDiv == 0)  in get_clocks()
139 		if (idiff == 0) {  in get_clocks()