6  * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
10  * Cache and TLB management
45 void flush_data_cache_local(void *);  /* flushes local data-cache only */
46 void flush_instruction_cache_local(void); /* flushes local code-cache only */
48 /* On some machines (i.e., ones with the Merced bus), there can be
50  * by software. We need a spinlock around all TLB flushes to ensure
113 	    test_bit(PG_dcache_dirty, &folio->flags)) {  in __update_cache()
114 		while (nr--)  in __update_cache()
116 		clear_bit(PG_dcache_dirty, &folio->flags);  in __update_cache()
118 		while (nr--)  in __update_cache()
127 	seq_printf(m, "I-cache\t\t: %ld KB\n",   in show_cache_info()
130 		snprintf(buf, 32, "%lu-way associative", cache_info.dc_loop);  in show_cache_info()
131 	seq_printf(m, "D-cache\t\t: %ld KB (%s%s, %s, alias=%d)\n",  in show_cache_info()
134 		(cache_info.dc_conf.cc_sh ? ", shared I/D":""),  in show_cache_info()
141 		cache_info.dt_conf.tc_sh ? " - shared with ITLB":""  in show_cache_info()
145 	/* BTLB - Block TLB */  in show_cache_info()
151 		"BTLB fix-entr.\t: %d instruction, %d data (%d combined)\n"  in show_cache_info()
152 		"BTLB var-entr.\t: %d instruction, %d data (%d combined)\n",  in show_cache_info()
232 	printk("D-TLB conf: sh %d page %d cst %d aid %d sr %d\n",  in parisc_cache_init()
239 	printk("I-TLB conf: sh %d page %d cst %d aid %d sr %d\n",  in parisc_cache_init()
250 			printk(KERN_WARNING "Unexpected TLB configuration. "  in parisc_cache_init()
251 			"Will flush I/D separately (could be optimized).\n");  in parisc_cache_init()
257 	 *	(1 << (cc_block-1)) * (cc_line << (4 + cnf.cc_shift))  in parisc_cache_init()
259 	 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023625.html  in parisc_cache_init()
260 	 * http://lists.parisc-linux.org/pipermail/parisc-linux/2004-June/023671.html  in parisc_cache_init()
267 	/* stride needs to be non-zero, otherwise cache flushes will not work */  in parisc_cache_init()
275 		panic("SMP kernel required to avoid non-equivalent aliasing");  in parisc_cache_init()
326 	if (vma->vm_flags & VM_EXEC)  in __flush_cache_page()
350 	switch_mm_irqs_off(NULL, vma->vm_mm, NULL);  in flush_user_cache_page()
354 	if (vma->vm_flags & VM_EXEC)  in flush_user_cache_page()
379 		if (--nr == 0)  in flush_icache_pages()
388 	pgd_t *pgd = mm->pgd;  in get_ptep()
420 	unsigned long i, nr, flags;  in flush_dcache_folio()  local
424 		set_bit(PG_dcache_dirty, &folio->flags);  in flush_dcache_folio()
430 	for (i = 0; i < nr; i++)  in flush_dcache_folio()
431 		flush_kernel_dcache_page_addr(kaddr + i * PAGE_SIZE);  in flush_dcache_folio()
436 	pgoff = folio->index;  in flush_dcache_folio()
446 	vma_interval_tree_foreach(vma, &mapping->i_mmap, pgoff, pgoff + nr - 1) {  in flush_dcache_folio()
447 		unsigned long offset = pgoff - vma->vm_pgoff;  in flush_dcache_folio()
450 		addr = vma->vm_start;  in flush_dcache_folio()
452 		if (offset > -nr) {  in flush_dcache_folio()
453 			pfn -= offset;  in flush_dcache_folio()
458 		if (addr + nr * PAGE_SIZE > vma->vm_end)  in flush_dcache_folio()
459 			nr = (vma->vm_end - addr) / PAGE_SIZE;  in flush_dcache_folio()
462 			for (i = 0; i < nr; i++) {  in flush_dcache_folio()
463 				pte_t *ptep = get_ptep(vma->vm_mm,  in flush_dcache_folio()
464 							addr + i * PAGE_SIZE);  in flush_dcache_folio()
469 							addr + i * PAGE_SIZE);  in flush_dcache_folio()
475 			 * The TLB is the engine of coherence on parisc:  in flush_dcache_folio()
477 			 * with a TLB mapping, so here we kill the  in flush_dcache_folio()
480 			 * the page is no-longer in the cache for any  in flush_dcache_folio()
485 			for (i = 0; i < nr; i++)  in flush_dcache_folio()
486 				flush_tlb_page(vma, addr + i * PAGE_SIZE);  in flush_dcache_folio()
487 			if (old_addr == 0 || (old_addr & (SHM_COLOUR - 1))  in flush_dcache_folio()
488 					!= (addr & (SHM_COLOUR - 1))) {  in flush_dcache_folio()
489 				for (i = 0; i < nr; i++)  in flush_dcache_folio()
491 						addr + i * PAGE_SIZE,  in flush_dcache_folio()
492 						(pfn + i) * PAGE_SIZE);  in flush_dcache_folio()
497 				if (!(vma->vm_flags & VM_SHARED))  in flush_dcache_folio()
501 						old_addr, addr, vma->vm_file);  in flush_dcache_folio()
519 #define FLUSH_TLB_THRESHOLD (16*1024) /* 16 KiB minimum TLB threshold */
525 	unsigned long size;  in parisc_setup_cache_timing()  local
530 	alltime = mfctl(16) - alltime;  in parisc_setup_cache_timing()
532 	size = (unsigned long)(_end - _text);  in parisc_setup_cache_timing()
534 	flush_kernel_dcache_range((unsigned long)_text, size);  in parisc_setup_cache_timing()
535 	rangetime = mfctl(16) - rangetime;  in parisc_setup_cache_timing()
538 		alltime, size, rangetime);  in parisc_setup_cache_timing()
540 	threshold = L1_CACHE_ALIGN((unsigned long)((uint64_t)size * alltime / rangetime));  in parisc_setup_cache_timing()
553 	/* calculate TLB flush threshold */  in parisc_setup_cache_timing()
555 	/* On SMP machines, skip the TLB measure of kernel text which  in parisc_setup_cache_timing()
564 	size = (unsigned long)_end - (unsigned long)_text;  in parisc_setup_cache_timing()
567 	rangetime = mfctl(16) - rangetime;  in parisc_setup_cache_timing()
571 	alltime = mfctl(16) - alltime;  in parisc_setup_cache_timing()
573 	printk(KERN_INFO "Whole TLB flush %lu cycles, Range flush %lu bytes %lu cycles\n",  in parisc_setup_cache_timing()
574 		alltime, size, rangetime);  in parisc_setup_cache_timing()
576 	threshold = PAGE_ALIGN((num_online_cpus() * size * alltime) / rangetime);  in parisc_setup_cache_timing()
577 	printk(KERN_INFO "Calculated TLB flush threshold %lu KiB\n",  in parisc_setup_cache_timing()
586 	printk(KERN_INFO "TLB flush threshold set to %lu KiB\n",  in parisc_setup_cache_timing()
613 	 * a non-access TLB miss. Hopefully, the page has already been  in flush_cache_page_if_present()
616 	ptep = get_ptep(vma->vm_mm, vmaddr);  in flush_cache_page_if_present()
663 	    end - start >= parisc_tlb_flush_threshold) {  in __flush_tlb_range()
668 	/* Purge TLB entries for small ranges using the pdtlb and  in __flush_tlb_range()
694 		ptep = get_ptep(vma->vm_mm, addr);  in flush_cache_pages()
721 		usize += vma->vm_end - vma->vm_start;  in mm_total_size()
750 		flush_cache_pages(vma, vma->vm_start, vma->vm_end);  in flush_cache_mm()
756 	    || end - start >= parisc_cache_flush_threshold) {  in flush_cache_range()
783 		if (vma->vm_flags & VM_SHARED)  in flush_anon_page()
796 void flush_kernel_vmap_range(void *vaddr, int size)  in flush_kernel_vmap_range()  argument
799 	unsigned long end = start + size;  in flush_kernel_vmap_range()
802 	    (unsigned long)size >= parisc_cache_flush_threshold) {  in flush_kernel_vmap_range()
813 void invalidate_kernel_vmap_range(void *vaddr, int size)  in invalidate_kernel_vmap_range()  argument
816 	unsigned long end = start + size;  in invalidate_kernel_vmap_range()
822 	    (unsigned long)size >= parisc_cache_flush_threshold) {  in invalidate_kernel_vmap_range()
843 		return -EFAULT;  in SYSCALL_DEFINE3()
859 			: "r" (end), "r" (dcache_stride), "i" (SR_USER));  in SYSCALL_DEFINE3()
874 			: "r" (end), "r" (icache_stride), "i" (SR_USER));  in SYSCALL_DEFINE3()