Lines Matching +full:32 +full:mb

26 /* Frame alignment for 32- and 64-bit */
62 #define LDREGM ldd,mb
134 zdep \r, 31-(\sa), 32-(\sa), \t
142 /* Shift Right for 32-bit. Clobbers upper 32-bit on PA2.0. */
144 extru \r, 31-(\sa), 32-(\sa), \t
152 /* Extract unsigned for 32- and 64-bit
153 * The extru instruction leaves the most significant 32 bits of the
157 extrd,u \r, 32+(\p), \len, \t
163 /* The depi instruction leaves the most significant 32 bits of the
167 depdi \i, 32+(\p), \len, \t
173 /* The depw instruction leaves the most significant 32 bits of the
177 depd \i, 32+(\p), \len, \t
183 /* load 32-bit 'value' into 'reg' compensating for the ldil
312 fldd,mb -8(\regs), %fr30
313 fldd,mb -8(\regs), %fr29
314 fldd,mb -8(\regs), %fr28
315 fldd,mb -8(\regs), %fr27
316 fldd,mb -8(\regs), %fr26
317 fldd,mb -8(\regs), %fr25
318 fldd,mb -8(\regs), %fr24
319 fldd,mb -8(\regs), %fr23
320 fldd,mb -8(\regs), %fr22
321 fldd,mb -8(\regs), %fr21
322 fldd,mb -8(\regs), %fr20
323 fldd,mb -8(\regs), %fr19
324 fldd,mb -8(\regs), %fr18
325 fldd,mb -8(\regs), %fr17
326 fldd,mb -8(\regs), %fr16
327 fldd,mb -8(\regs), %fr15
328 fldd,mb -8(\regs), %fr14
329 fldd,mb -8(\regs), %fr13
330 fldd,mb -8(\regs), %fr12
331 fldd,mb -8(\regs), %fr11
332 fldd,mb -8(\regs), %fr10
333 fldd,mb -8(\regs), %fr9
334 fldd,mb -8(\regs), %fr8
335 fldd,mb -8(\regs), %fr7
336 fldd,mb -8(\regs), %fr6
337 fldd,mb -8(\regs), %fr5
338 fldd,mb -8(\regs), %fr4
339 fldd,mb -8(\regs), %fr3
340 fldd,mb -8(\regs), %fr2
341 fldd,mb -8(\regs), %fr1
342 fldd,mb -8(\regs), %fr0
359 fldd,mb -8(%r30), %fr21
360 fldd,mb -8(%r30), %fr20
361 fldd,mb -8(%r30), %fr19
362 fldd,mb -8(%r30), %fr18
363 fldd,mb -8(%r30), %fr17
364 fldd,mb -8(%r30), %fr16
365 fldd,mb -8(%r30), %fr15
366 fldd,mb -8(%r30), %fr14
367 fldd,mb -8(%r30), %fr13
368 fldd,mb -8(%r30), %fr12
388 std %r17, -32(%r30)
396 ldd -32(%r30), %r17
411 ldd,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3
455 ldw,mb -CALLEE_REG_FRAME_SIZE(%r30), %r3