60 	if (i == 0)  in print_data()
84 		in_kernel = 0;  in show_registers()
91 	       0L, regs->gpr[1], regs->gpr[2], regs->gpr[3]);  in show_registers()
160 	printk("\n%s#: %04lx\n", str, err & 0xffff);  in die()
176 	printk("Unable to handle exception at EA =0x%x, vector 0x%x",  in unhandled_exception()
214 		printk("KERNEL: Unaligned Access 0x%.8lx\n", address);  in do_unaligned_access()
227 		printk("KERNEL: Bus error (SIGBUS) 0x%.8lx\n", address);  in do_bus_fault()
242 	case 0x00: /* l.j */  in in_delay_slot()
243 	case 0x01: /* l.jal */  in in_delay_slot()
244 	case 0x03: /* l.bnf */  in in_delay_slot()
245 	case 0x04: /* l.bf */  in in_delay_slot()
246 	case 0x11: /* l.jr */  in in_delay_slot()
247 	case 0x12: /* l.jalr */  in in_delay_slot()
250 		return 0;  in in_delay_slot()
266 		displacement = sign_extend32(((jmp) & 0x3ffffff) << 2, 27);  in adjust_pc()
267 		rb = (jmp & 0x0000ffff) >> 11;  in adjust_pc()
271 		case 0x00: /* l.j */  in adjust_pc()
274 		case 0x01: /* l.jal */  in adjust_pc()
278 		case 0x03: /* l.bnf */  in adjust_pc()
284 		case 0x04: /* l.bf */  in adjust_pc()
290 		case 0x11: /* l.jr */  in adjust_pc()
293 		case 0x12: /* l.jalr */  in adjust_pc()
318 	ra = (insn >> 16) & 0x1f;  in simulate_lwa()
319 	rd = (insn >> 21) & 0x1f;  in simulate_lwa()
323 	if ((unsigned long)lwa_addr & 0x3) {  in simulate_lwa()
360 	ra = (insn >> 16) & 0x1f;  in simulate_swa()
361 	rb = (insn >> 11) & 0x1f;  in simulate_swa()
362 	imm = (short)(((insn & 0x2200000) >> 10) | (insn & 0x7ff));  in simulate_swa()
370 	if ((unsigned long)vaddr & 0x3) {  in simulate_swa()
390 	lwa_flag = 0;  in simulate_swa()
394 #define INSN_LWA	0x1b
395 #define INSN_SWA	0x33
422 		printk("KERNEL: Illegal instruction (SIGILL) 0x%.8lx\n",  in do_illegal_instruction()