Lines Matching +full:- +full:l
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
25 #include <asm/asm-offsets.h>
28 l.mfspr t2,r0,SPR_SR ;\
29 l.movhi t1,hi(~(SPR_SR_IEE|SPR_SR_TEE)) ;\
30 l.ori t1,t1,lo(~(SPR_SR_IEE|SPR_SR_TEE)) ;\
31 l.and t2,t2,t1 ;\
32 l.mtspr r0,t2,SPR_SR
35 l.mfspr t1,r0,SPR_SR ;\
36 l.ori t1,t1,lo(SPR_SR_IEE|SPR_SR_TEE) ;\
37 l.mtspr r0,t1,SPR_SR
46 l.sw -8(r1),r2 /* store frame pointer */ ;\
47 l.sw -4(r1),r9 /* store return address */ ;\
48 l.addi r2,r1,0 /* move sp to fp */ ;\
49 l.jal trace_op ;\
50 l.addi r1,r1,-8 ;\
51 l.ori r1,r2,0 /* restore sp */ ;\
52 l.lwz r9,-4(r1) /* restore return address */ ;\
53 l.lwz r2,-8(r1) /* restore fp */ ;\
59 l.sw -12(r1),t1 /* save extra reg */ ;\
60 l.sw -8(r1),r2 /* store frame pointer */ ;\
61 l.sw -4(r1),r9 /* store return address */ ;\
62 l.addi r2,r1,0 /* move sp to fp */ ;\
63 l.jal trace_op ;\
64 l.addi r1,r1,-12 ;\
65 l.ori r1,r2,0 /* restore sp */ ;\
66 l.lwz r9,-4(r1) /* restore return address */ ;\
67 l.lwz r2,-8(r1) /* restore fp */ ;\
68 l.lwz t1,-12(r1) /* restore extra reg */
74 l.lwz r3,PT_GPR3(r1) ;\
75 l.lwz r4,PT_GPR4(r1) ;\
76 l.lwz r5,PT_GPR5(r1) ;\
77 l.lwz r6,PT_GPR6(r1) ;\
78 l.lwz r7,PT_GPR7(r1) ;\
79 l.lwz r8,PT_GPR8(r1) ;\
80 l.lwz r11,PT_GPR11(r1)
82 l.lwz r5,PT_SR(r1) ;\
83 l.andi r3,r5,(SPR_SR_IEE|SPR_SR_TEE) ;\
84 l.sfeq r5,r0 /* skip trace if irqs were already off */;\
85 l.bf 1f ;\
86 l.nop ;\
105 l.lwz r3,PT_PC(r1) ;\
106 l.mtspr r0,r3,SPR_EPCR_BASE ;\
107 l.lwz r3,PT_SR(r1) ;\
108 l.mtspr r0,r3,SPR_ESR_BASE ;\
109 l.lwz r3,PT_FPCSR(r1) ;\
110 l.mtspr r0,r3,SPR_FPCSR ;\
111 l.lwz r2,PT_GPR2(r1) ;\
112 l.lwz r3,PT_GPR3(r1) ;\
113 l.lwz r4,PT_GPR4(r1) ;\
114 l.lwz r5,PT_GPR5(r1) ;\
115 l.lwz r6,PT_GPR6(r1) ;\
116 l.lwz r7,PT_GPR7(r1) ;\
117 l.lwz r8,PT_GPR8(r1) ;\
118 l.lwz r9,PT_GPR9(r1) ;\
119 l.lwz r10,PT_GPR10(r1) ;\
120 l.lwz r11,PT_GPR11(r1) ;\
121 l.lwz r12,PT_GPR12(r1) ;\
122 l.lwz r13,PT_GPR13(r1) ;\
123 l.lwz r14,PT_GPR14(r1) ;\
124 l.lwz r15,PT_GPR15(r1) ;\
125 l.lwz r16,PT_GPR16(r1) ;\
126 l.lwz r17,PT_GPR17(r1) ;\
127 l.lwz r18,PT_GPR18(r1) ;\
128 l.lwz r19,PT_GPR19(r1) ;\
129 l.lwz r20,PT_GPR20(r1) ;\
130 l.lwz r21,PT_GPR21(r1) ;\
131 l.lwz r22,PT_GPR22(r1) ;\
132 l.lwz r23,PT_GPR23(r1) ;\
133 l.lwz r24,PT_GPR24(r1) ;\
134 l.lwz r25,PT_GPR25(r1) ;\
135 l.lwz r26,PT_GPR26(r1) ;\
136 l.lwz r27,PT_GPR27(r1) ;\
137 l.lwz r28,PT_GPR28(r1) ;\
138 l.lwz r29,PT_GPR29(r1) ;\
139 l.lwz r30,PT_GPR30(r1) ;\
140 l.lwz r31,PT_GPR31(r1) ;\
141 l.lwz r1,PT_SP(r1) ;\
142 l.rfe
149 l.sw PT_GPR2(r1),r2 ;\
150 l.sw PT_GPR3(r1),r3 ;\
152 l.sw PT_GPR5(r1),r5 ;\
153 l.sw PT_GPR6(r1),r6 ;\
154 l.sw PT_GPR7(r1),r7 ;\
155 l.sw PT_GPR8(r1),r8 ;\
156 l.sw PT_GPR9(r1),r9 ;\
158 l.sw PT_GPR11(r1),r11 ;\
160 l.sw PT_GPR13(r1),r13 ;\
161 l.sw PT_GPR14(r1),r14 ;\
162 l.sw PT_GPR15(r1),r15 ;\
163 l.sw PT_GPR16(r1),r16 ;\
164 l.sw PT_GPR17(r1),r17 ;\
165 l.sw PT_GPR18(r1),r18 ;\
166 l.sw PT_GPR19(r1),r19 ;\
167 l.sw PT_GPR20(r1),r20 ;\
168 l.sw PT_GPR21(r1),r21 ;\
169 l.sw PT_GPR22(r1),r22 ;\
170 l.sw PT_GPR23(r1),r23 ;\
171 l.sw PT_GPR24(r1),r24 ;\
172 l.sw PT_GPR25(r1),r25 ;\
173 l.sw PT_GPR26(r1),r26 ;\
174 l.sw PT_GPR27(r1),r27 ;\
175 l.sw PT_GPR28(r1),r28 ;\
176 l.sw PT_GPR29(r1),r29 ;\
178 l.sw PT_GPR31(r1),r31 ;\
180 l.mfspr r30,r0,SPR_FPCSR ;\
181 l.sw PT_FPCSR(r1),r30 ;\
182 /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
183 l.addi r30,r0,-1 ;\
184 l.sw PT_ORIG_GPR11(r1),r30
190 l.sw PT_GPR2(r1),r2 ;\
191 l.sw PT_GPR3(r1),r3 ;\
192 l.sw PT_GPR5(r1),r5 ;\
193 l.sw PT_GPR6(r1),r6 ;\
194 l.sw PT_GPR7(r1),r7 ;\
195 l.sw PT_GPR8(r1),r8 ;\
196 l.sw PT_GPR9(r1),r9 ;\
198 l.sw PT_GPR11(r1),r11 ;\
200 l.sw PT_GPR13(r1),r13 ;\
201 l.sw PT_GPR14(r1),r14 ;\
202 l.sw PT_GPR15(r1),r15 ;\
203 l.sw PT_GPR16(r1),r16 ;\
204 l.sw PT_GPR17(r1),r17 ;\
205 l.sw PT_GPR18(r1),r18 ;\
206 l.sw PT_GPR19(r1),r19 ;\
207 l.sw PT_GPR20(r1),r20 ;\
208 l.sw PT_GPR21(r1),r21 ;\
209 l.sw PT_GPR22(r1),r22 ;\
210 l.sw PT_GPR23(r1),r23 ;\
211 l.sw PT_GPR24(r1),r24 ;\
212 l.sw PT_GPR25(r1),r25 ;\
213 l.sw PT_GPR26(r1),r26 ;\
214 l.sw PT_GPR27(r1),r27 ;\
215 l.sw PT_GPR28(r1),r28 ;\
216 l.sw PT_GPR29(r1),r29 ;\
218 l.sw PT_GPR31(r1),r31 ;\
219 /* Store -1 in orig_gpr11 for non-syscall exceptions */ ;\
220 l.addi r30,r0,-1 ;\
221 l.sw PT_ORIG_GPR11(r1),r30 ;\
222 l.mfspr r30,r0,SPR_FPCSR ;\
223 l.sw PT_FPCSR(r1),r30 ;\
224 l.addi r3,r1,0 ;\
226 l.addi r5,r0,vector ;\
227 l.jal unhandled_exception ;\
228 l.nop ;\
229 l.j _ret_from_exception ;\
230 l.nop
234 l.movhi reg,hi(lwa_flag) ;\
235 l.ori reg,reg,lo(lwa_flag) ;\
236 l.sw 0(reg),r0
248 /* ---[ 0x100: RESET exception ]----------------------------------------- */
251 l.jal _start
252 l.andi r0,r0,0
254 /* ---[ 0x200: BUS exception ]------------------------------------------- */
259 l.jal do_bus_fault
260 l.addi r3,r1,0 /* pt_regs */
262 l.j _ret_from_exception
263 l.nop
265 /* ---[ 0x300: Data Page Fault exception ]------------------------------- */
268 l.and r5,r5,r0
269 l.j 1f
270 l.nop
275 l.ori r5,r0,0x300 // exception vector
277 l.addi r3,r1,0 // pt_regs
281 l.lwz r6,PT_PC(r3) // address of an offending insn
282 l.lwz r6,0(r6) // instruction that caused pf
284 l.srli r6,r6,26 // check opcode for jump insn
285 l.sfeqi r6,0 // l.j
286 l.bf 8f
287 l.sfeqi r6,1 // l.jal
288 l.bf 8f
289 l.sfeqi r6,3 // l.bnf
290 l.bf 8f
291 l.sfeqi r6,4 // l.bf
292 l.bf 8f
293 l.sfeqi r6,0x11 // l.jr
294 l.bf 8f
295 l.sfeqi r6,0x12 // l.jalr
296 l.bf 8f
297 l.nop
299 l.j 9f
300 l.nop
303 l.lwz r6,PT_PC(r3) // address of an offending insn
304 l.addi r6,r6,4
305 l.lwz r6,0(r6) // instruction that caused pf
306 l.srli r6,r6,26 // get opcode
311 l.mfspr r6,r0,SPR_SR // SR
312 l.andi r6,r6,SPR_SR_DSX // check for delay slot exception
313 l.sfne r6,r0 // exception happened in delay slot
314 l.bnf 7f
315 l.lwz r6,PT_PC(r3) // address of an offending insn
317 l.addi r6,r6,4 // offending insn is in delay slot
319 l.lwz r6,0(r6) // instruction that caused pf
320 l.srli r6,r6,26 // check opcode for write access
323 l.sfgeui r6,0x33 // check opcode for write access
324 l.bnf 1f
325 l.sfleui r6,0x37
326 l.bnf 1f
327 l.ori r6,r0,0x1 // write access
328 l.j 2f
329 l.nop
330 1: l.ori r6,r0,0x0 // !write access
334 l.jal do_page_fault
335 l.nop
336 l.j _ret_from_exception
337 l.nop
339 /* ---[ 0x400: Insn Page Fault exception ]------------------------------- */
342 l.and r5,r5,r0
343 l.j 1f
344 l.nop
349 l.ori r5,r0,0x400 // exception vector
351 l.addi r3,r1,0 // pt_regs
353 l.ori r6,r0,0x0 // !write access
356 l.jal do_page_fault
357 l.nop
358 l.j _ret_from_exception
359 l.nop
362 /* ---[ 0x500: Timer exception ]----------------------------------------- */
366 l.jal timer_interrupt
367 l.addi r3,r1,0 /* pt_regs */
369 l.j _ret_from_intr
370 l.nop
372 /* ---[ 0x600: Alignment exception ]-------------------------------------- */
377 l.jal do_unaligned_access
378 l.addi r3,r1,0 /* pt_regs */
380 l.j _ret_from_exception
381 l.nop
385 // l.mfspr r2,r0,SPR_EEAR_BASE /* Load the effective address */
386 l.addi r2,r4,0
387 // l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */
388 l.lwz r5,PT_PC(r1)
390 l.lwz r3,0(r5) /* Load insn */
391 l.srli r4,r3,26 /* Shift left to get the insn opcode */
393 l.sfeqi r4,0x00 /* Check if the load/store insn is in delay slot */
394 l.bf jmp
395 l.sfeqi r4,0x01
396 l.bf jmp
397 l.sfeqi r4,0x03
398 l.bf jmp
399 l.sfeqi r4,0x04
400 l.bf jmp
401 l.sfeqi r4,0x11
402 l.bf jr
403 l.sfeqi r4,0x12
404 l.bf jr
405 l.nop
406 l.j 1f
407 l.addi r5,r5,4 /* Increment PC to get return insn address */
410 l.slli r4,r3,6 /* Get the signed extended jump length */
411 l.srai r4,r4,4
413 l.lwz r3,4(r5) /* Load the real load/store insn */
415 l.add r5,r5,r4 /* Calculate jump target address */
417 l.j 1f
418 l.srli r4,r3,26 /* Shift left to get the insn opcode */
421 l.slli r4,r3,9 /* Shift to get the reg nb */
422 l.andi r4,r4,0x7c
424 l.lwz r3,4(r5) /* Load the real load/store insn */
426 l.add r4,r4,r1 /* Load the jump register value from the stack */
427 l.lwz r5,0(r4)
429 l.srli r4,r3,26 /* Shift left to get the insn opcode */
433 // l.mtspr r0,r5,SPR_EPCR_BASE
434 l.sw PT_PC(r1),r5
436 l.sfeqi r4,0x26
437 l.bf lhs
438 l.sfeqi r4,0x25
439 l.bf lhz
440 l.sfeqi r4,0x22
441 l.bf lws
442 l.sfeqi r4,0x21
443 l.bf lwz
444 l.sfeqi r4,0x37
445 l.bf sh
446 l.sfeqi r4,0x35
447 l.bf sw
448 l.nop
450 1: l.j 1b /* I don't know what to do */
451 l.nop
453 lhs: l.lbs r5,0(r2)
454 l.slli r5,r5,8
455 l.lbz r6,1(r2)
456 l.or r5,r5,r6
457 l.srli r4,r3,19
458 l.andi r4,r4,0x7c
459 l.add r4,r4,r1
460 l.j align_end
461 l.sw 0(r4),r5
463 lhz: l.lbz r5,0(r2)
464 l.slli r5,r5,8
465 l.lbz r6,1(r2)
466 l.or r5,r5,r6
467 l.srli r4,r3,19
468 l.andi r4,r4,0x7c
469 l.add r4,r4,r1
470 l.j align_end
471 l.sw 0(r4),r5
473 lws: l.lbs r5,0(r2)
474 l.slli r5,r5,24
475 l.lbz r6,1(r2)
476 l.slli r6,r6,16
477 l.or r5,r5,r6
478 l.lbz r6,2(r2)
479 l.slli r6,r6,8
480 l.or r5,r5,r6
481 l.lbz r6,3(r2)
482 l.or r5,r5,r6
483 l.srli r4,r3,19
484 l.andi r4,r4,0x7c
485 l.add r4,r4,r1
486 l.j align_end
487 l.sw 0(r4),r5
489 lwz: l.lbz r5,0(r2)
490 l.slli r5,r5,24
491 l.lbz r6,1(r2)
492 l.slli r6,r6,16
493 l.or r5,r5,r6
494 l.lbz r6,2(r2)
495 l.slli r6,r6,8
496 l.or r5,r5,r6
497 l.lbz r6,3(r2)
498 l.or r5,r5,r6
499 l.srli r4,r3,19
500 l.andi r4,r4,0x7c
501 l.add r4,r4,r1
502 l.j align_end
503 l.sw 0(r4),r5
506 l.srli r4,r3,9
507 l.andi r4,r4,0x7c
508 l.add r4,r4,r1
509 l.lwz r5,0(r4)
510 l.sb 1(r2),r5
511 l.srli r5,r5,8
512 l.j align_end
513 l.sb 0(r2),r5
516 l.srli r4,r3,9
517 l.andi r4,r4,0x7c
518 l.add r4,r4,r1
519 l.lwz r5,0(r4)
520 l.sb 3(r2),r5
521 l.srli r5,r5,8
522 l.sb 2(r2),r5
523 l.srli r5,r5,8
524 l.sb 1(r2),r5
525 l.srli r5,r5,8
526 l.j align_end
527 l.sb 0(r2),r5
530 l.j _ret_from_intr
531 l.nop
534 /* ---[ 0x700: Illegal insn exception ]---------------------------------- */
538 l.jal do_illegal_instruction
539 l.addi r3,r1,0 /* pt_regs */
541 l.j _ret_from_exception
542 l.nop
544 /* ---[ 0x800: External interrupt exception ]---------------------------- */
548 l.lwz r4,PT_SR(r1) // were interrupts enabled ?
549 l.andi r4,r4,SPR_SR_IEE
550 l.sfeqi r4,0
551 l.bnf 1f // ext irq enabled, all ok.
552 l.nop
555 l.addi r1,r1,-0x8
556 l.movhi r3,hi(42f)
557 l.ori r3,r3,lo(42f)
558 l.sw 0x0(r1),r3
559 l.jal _printk
560 l.sw 0x4(r1),r4
561 l.addi r1,r1,0x8
570 l.ori r4,r4,SPR_SR_IEE // fix the bug
571 // l.sw PT_SR(r1),r4
575 l.addi r3,r1,0
576 l.movhi r8,hi(generic_handle_arch_irq)
577 l.ori r8,r8,lo(generic_handle_arch_irq)
578 l.jalr r8
579 l.nop
580 l.j _ret_from_intr
581 l.nop
583 /* ---[ 0x900: DTLB miss exception ]------------------------------------- */
586 /* ---[ 0xa00: ITLB miss exception ]------------------------------------- */
589 /* ---[ 0xb00: Range exception ]----------------------------------------- */
593 /* ---[ 0xc00: Syscall exception ]--------------------------------------- */
603 /* Upon syscall entry we just save the callee-saved registers
604 * and not the call-clobbered ones.
608 .string "syscall r9:0x%08x -> syscall(%ld) return %ld\0"
613 l.sw PT_GPR2(r1),r2
614 /* r3-r8 must be saved because syscall restart relies
618 l.sw PT_GPR3(r1),r3
625 l.lwz r4,PT_GPR4(r1)
626 l.sw PT_GPR5(r1),r5
627 l.sw PT_GPR6(r1),r6
628 l.sw PT_GPR7(r1),r7
629 l.sw PT_GPR8(r1),r8
630 l.sw PT_GPR9(r1),r9
632 l.sw PT_GPR11(r1),r11
634 l.sw PT_ORIG_GPR11(r1),r11
637 /* r14-r28 (even) aren't touched by the syscall fast path below
646 /* l.sw PT_GPR30(r1),r30 */
654 l.lwz r30,TI_FLAGS(r10)
655 l.andi r30,r30,_TIF_SYSCALL_TRACE
656 l.sfne r30,r0
657 l.bf _syscall_trace_enter
658 l.nop
662 l.sfgeui r11,__NR_syscalls
663 l.bf _syscall_badsys
664 l.nop
667 l.movhi r29,hi(sys_call_table)
668 l.ori r29,r29,lo(sys_call_table)
669 l.slli r11,r11,2
670 l.add r29,r29,r11
671 l.lwz r29,0(r29)
673 l.jalr r29
674 l.nop
678 * which does it in a round-about way.
680 l.sw PT_GPR11(r1),r11 // save return value
684 l.movhi r3,hi(_string_syscall_return)
685 l.ori r3,r3,lo(_string_syscall_return)
686 l.ori r27,r0,2
687 l.sw -4(r1),r27
688 l.sw -8(r1),r11
689 l.lwz r29,PT_ORIG_GPR11(r1)
690 l.sw -12(r1),r29
691 l.lwz r29,PT_GPR9(r1)
692 l.sw -16(r1),r29
693 l.movhi r27,hi(_printk)
694 l.ori r27,r27,lo(_printk)
695 l.jalr r27
696 l.addi r1,r1,-16
697 l.addi r1,r1,16
701 l.movhi r27,hi(show_registers)
702 l.ori r27,r27,lo(show_registers)
703 l.jalr r27
704 l.or r3,r1,r1
708 /* r30 is a callee-saved register so this should still hold the
710 * _syscall_trace_leave expects syscall result to be in pt_regs->r11.
712 l.sfne r30,r0
713 l.bf _syscall_trace_leave
714 l.nop
716 /* This is where the exception-return code begins... interrupts need to be
724 l.lwz r30,TI_FLAGS(r10)
725 l.andi r30,r30,_TIF_WORK_MASK
726 l.sfne r30,r0
728 l.bnf _syscall_resume_userspace
729 l.nop
732 * make sure that all the call-saved registers get into pt_regs
735 l.sw PT_GPR14(r1),r14
736 l.sw PT_GPR16(r1),r16
737 l.sw PT_GPR18(r1),r18
738 l.sw PT_GPR20(r1),r20
739 l.sw PT_GPR22(r1),r22
740 l.sw PT_GPR24(r1),r24
741 l.sw PT_GPR26(r1),r26
742 l.sw PT_GPR28(r1),r28
745 l.j _work_pending
746 l.nop
756 * registers with whatever garbage is in pt_regs -- that's OK because those
763 /* The assumption here is that the registers r14-r28 (even) are untouched and
772 l.lwz r2,PT_GPR2(r1)
775 /* r3-r8 are technically clobbered, but syscall restart needs these
778 l.lwz r3,PT_GPR3(r1)
779 l.lwz r4,PT_GPR4(r1)
780 l.lwz r5,PT_GPR5(r1)
781 l.lwz r6,PT_GPR6(r1)
782 l.lwz r7,PT_GPR7(r1)
783 l.lwz r8,PT_GPR8(r1)
785 l.lwz r9,PT_GPR9(r1)
786 l.lwz r10,PT_GPR10(r1)
787 l.lwz r11,PT_GPR11(r1)
790 l.lwz r30,PT_GPR30(r1)
792 /* Here we use r13-r19 (odd) as scratch regs */
793 l.lwz r13,PT_PC(r1)
794 l.lwz r15,PT_SR(r1)
795 l.lwz r1,PT_SP(r1)
798 * them before we can use them for our l.rfe */
800 l.mtspr r0,r13,SPR_EPCR_BASE
801 l.mtspr r0,r15,SPR_ESR_BASE
802 l.rfe
816 l.jal do_syscall_trace_enter
817 l.addi r3,r1,0
823 l.lwz r11,PT_GPR11(r1)
824 l.lwz r3,PT_GPR3(r1)
825 l.lwz r4,PT_GPR4(r1)
826 l.lwz r5,PT_GPR5(r1)
827 l.lwz r6,PT_GPR6(r1)
828 l.lwz r7,PT_GPR7(r1)
830 l.j _syscall_check
831 l.lwz r8,PT_GPR8(r1)
834 l.jal do_syscall_trace_leave
835 l.addi r3,r1,0
837 l.j _syscall_check_work
838 l.nop
842 * syscall that returns -ENOSYS and then return to the regular
846 l.j _syscall_return
847 l.addi r11,r0,-ENOSYS
851 /* ---[ 0xd00: Floating Point exception ]-------------------------------- */
856 l.jal do_fpe_trap
857 l.addi r3,r1,0 /* pt_regs */
859 l.j _ret_from_exception
860 l.nop
862 /* ---[ 0xe00: Trap exception ]------------------------------------------ */
867 l.jal do_trap
868 l.addi r3,r1,0 /* pt_regs */
870 l.j _ret_from_exception
871 l.nop
873 /* ---[ 0xf00: Reserved exception ]-------------------------------------- */
877 /* ---[ 0x1000: Reserved exception ]------------------------------------- */
881 /* ---[ 0x1100: Reserved exception ]------------------------------------- */
885 /* ---[ 0x1200: Reserved exception ]------------------------------------- */
889 /* ---[ 0x1300: Reserved exception ]------------------------------------- */
893 /* ---[ 0x1400: Reserved exception ]------------------------------------- */
897 /* ---[ 0x1500: Reserved exception ]------------------------------------- */
901 /* ---[ 0x1600: Reserved exception ]------------------------------------- */
905 /* ---[ 0x1700: Reserved exception ]------------------------------------- */
909 /* ---[ 0x1800: Reserved exception ]------------------------------------- */
913 /* ---[ 0x1900: Reserved exception ]------------------------------------- */
917 /* ---[ 0x1a00: Reserved exception ]------------------------------------- */
921 /* ---[ 0x1b00: Reserved exception ]------------------------------------- */
925 /* ---[ 0x1c00: Reserved exception ]------------------------------------- */
929 /* ---[ 0x1d00: Reserved exception ]------------------------------------- */
933 /* ---[ 0x1e00: Reserved exception ]------------------------------------- */
937 /* ---[ 0x1f00: Reserved exception ]------------------------------------- */
946 l.lwz r4,TI_FLAGS(r10)
947 l.andi r13,r4,_TIF_WORK_MASK
948 l.sfeqi r13,0
949 l.bf _restore_all
950 l.nop
953 l.lwz r5,PT_ORIG_GPR11(r1)
954 l.sfltsi r5,0
955 l.bnf 1f
956 l.nop
957 l.andi r5,r5,0
959 l.jal do_work_pending
960 l.ori r3,r1,0 /* pt_regs */
962 l.sfeqi r11,0
963 l.bf _restore_all
964 l.nop
965 l.sfltsi r11,0
966 l.bnf 1f
967 l.nop
968 l.and r11,r11,r0
969 l.ori r11,r11,__NR_restart_syscall
970 l.j _syscall_check_trace_enter
971 l.nop
973 l.lwz r11,PT_ORIG_GPR11(r1)
975 l.lwz r3,PT_GPR3(r1)
976 l.lwz r4,PT_GPR4(r1)
977 l.lwz r5,PT_GPR5(r1)
978 l.lwz r6,PT_GPR6(r1)
979 l.lwz r7,PT_GPR7(r1)
980 l.j _syscall_check_trace_enter
981 l.lwz r8,PT_GPR8(r1)
985 l.lwz r4,PT_SR(r1)
986 l.andi r3,r4,(SPR_SR_IEE|SPR_SR_TEE)
987 l.sfeq r3,r0 /* skip trace if irqs were off */
988 l.bf skip_hardirqs_on
989 l.nop
999 l.lwz r4,PT_SR(r1)
1000 l.andi r3,r4,SPR_SR_SM
1001 l.sfeqi r3,0
1002 l.bnf _restore_all
1003 l.nop
1004 l.j _resume_userspace
1005 l.nop
1008 l.jal schedule_tail
1009 l.nop
1012 l.sfeqi r20,0
1013 l.bf 1f
1014 l.nop
1017 l.jalr r20
1018 l.or r3,r22,r0
1022 l.lwz r11,PT_GPR11(r1)
1024 /* The syscall fast path return expects call-saved registers
1025 * r14-r28 to be untouched, so we restore them here as they
1029 l.lwz r14,PT_GPR14(r1)
1030 l.lwz r16,PT_GPR16(r1)
1031 l.lwz r18,PT_GPR18(r1)
1032 l.lwz r20,PT_GPR20(r1)
1033 l.lwz r22,PT_GPR22(r1)
1034 l.lwz r24,PT_GPR24(r1)
1035 l.lwz r26,PT_GPR26(r1)
1036 l.lwz r28,PT_GPR28(r1)
1038 l.j _syscall_return
1039 l.nop
1065 * the l.rfe instruction. If get TLB miss in beetwen the EPCR register gets
1066 * garbled and we end up calling l.rfe with the wrong EPCR. (same probably
1075 * way, we are a function call and only need to preserve the callee-saved
1086 l.addi r1,r1,-(INT_FRAME_SIZE)
1089 l.sw PT_GPR2(r1),r2
1090 l.sw PT_GPR9(r1),r9
1092 /* Save callee-saved registers to the new pt_regs */
1093 l.sw PT_GPR14(r1),r14
1094 l.sw PT_GPR16(r1),r16
1095 l.sw PT_GPR18(r1),r18
1096 l.sw PT_GPR20(r1),r20
1097 l.sw PT_GPR22(r1),r22
1098 l.sw PT_GPR24(r1),r24
1099 l.sw PT_GPR26(r1),r26
1100 l.sw PT_GPR28(r1),r28
1101 l.sw PT_GPR30(r1),r30
1104 l.mfspr r29,r0,SPR_FPCSR
1105 l.sw PT_FPCSR(r1),r29
1107 l.addi r11,r10,0 /* Save old 'current' to 'last' return value*/
1109 /* We use thread_info->ksp for storing the address of the above
1111 * to lose the value of thread_info->ksp, though, so store it as
1112 * pt_regs->sp so that we can easily restore it when we are made
1116 /* Save the old value of thread_info->ksp as pt_regs->sp */
1117 l.lwz r29,TI_KSP(r10)
1118 l.sw PT_SP(r1),r29
1121 l.sw TI_KSP(r10),r1 /* Save old stack pointer */
1122 l.or r10,r4,r0 /* Set up new current_thread_info */
1123 l.lwz r1,TI_KSP(r10) /* Load new stack pointer */
1125 /* Restore the old value of thread_info->ksp */
1126 l.lwz r29,PT_SP(r1)
1127 l.sw TI_KSP(r10),r29
1130 l.lwz r29,PT_FPCSR(r1)
1131 l.mtspr r0,r29,SPR_FPCSR
1136 l.lwz r2,PT_GPR2(r1)
1137 l.lwz r9,PT_GPR9(r1)
1141 /* Restore callee-saved registers */
1142 l.lwz r14,PT_GPR14(r1)
1143 l.lwz r16,PT_GPR16(r1)
1144 l.lwz r18,PT_GPR18(r1)
1145 l.lwz r20,PT_GPR20(r1)
1146 l.lwz r22,PT_GPR22(r1)
1147 l.lwz r24,PT_GPR24(r1)
1148 l.lwz r26,PT_GPR26(r1)
1149 l.lwz r28,PT_GPR28(r1)
1150 l.lwz r30,PT_GPR30(r1)
1152 /* Unwind stack to pre-switch state */
1153 l.addi r1,r1,(INT_FRAME_SIZE)
1155 /* Return via the link-register back to where we 'came from', where
1161 l.lwz r3,TI_TASK(r3) /* Load 'prev' as schedule_tail arg */
1162 l.jr r9
1163 l.nop
1168 * jump is always happening after the l.addi instruction.
1170 * These are all just wrappers that don't touch the link-register r9, so the
1172 * code that did the l.jal that brought us here.
1175 /* fork requires that we save all the callee-saved registers because they
1182 l.sw PT_GPR14(r1),r14
1183 l.sw PT_GPR16(r1),r16
1184 l.sw PT_GPR18(r1),r18
1185 l.sw PT_GPR20(r1),r20
1186 l.sw PT_GPR22(r1),r22
1187 l.sw PT_GPR24(r1),r24
1188 l.sw PT_GPR26(r1),r26
1189 l.jr r29
1190 l.sw PT_GPR28(r1),r28
1193 l.movhi r29,hi(sys_clone)
1194 l.j _fork_save_extra_regs_and_call
1195 l.ori r29,r29,lo(sys_clone)
1198 l.movhi r29,hi(sys_clone3)
1199 l.j _fork_save_extra_regs_and_call
1200 l.ori r29,r29,lo(sys_clone3)
1203 l.movhi r29,hi(sys_fork)
1204 l.j _fork_save_extra_regs_and_call
1205 l.ori r29,r29,lo(sys_fork)
1208 l.jal _sys_rt_sigreturn
1209 l.addi r3,r1,0
1210 l.sfne r30,r0
1211 l.bnf _no_syscall_trace
1212 l.nop
1213 l.jal do_syscall_trace_leave
1214 l.addi r3,r1,0
1216 l.j _resume_userspace
1217 l.nop
1219 /* This is a catch-all syscall for atomic instructions for the OpenRISC 1000.
1236 l.lwz r29,0(r4)
1237 l.lwz r27,0(r5)
1238 l.sw 0(r4),r27
1239 l.sw 0(r5),r29
1241 l.jr r9
1242 l.or r11,r0,r0