Lines Matching +full:conditional +full:- +full:select
1 # SPDX-License-Identifier: GPL-2.0
4 # see Documentation/kbuild/kconfig-language.rst.
9 select ARCH_32BIT_OFF_T
10 select ARCH_HAS_DMA_SET_UNCACHED
11 select ARCH_HAS_DMA_CLEAR_UNCACHED
12 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
13 select COMMON_CLK
14 select OF
15 select OF_EARLY_FLATTREE
16 select IRQ_DOMAIN
17 select GPIOLIB
18 select HAVE_ARCH_TRACEHOOK
19 select SPARSE_IRQ
20 select GENERIC_IRQ_CHIP
21 select GENERIC_IRQ_PROBE
22 select GENERIC_IRQ_SHOW
23 select GENERIC_PCI_IOMAP
24 select GENERIC_IOREMAP
25 select GENERIC_CPU_DEVICES
26 select HAVE_PCI
27 select HAVE_UID16
28 select GENERIC_ATOMIC64
29 select GENERIC_CLOCKEVENTS_BROADCAST
30 select GENERIC_SMP_IDLE_THREAD
31 select MODULES_USE_ELF_RELA
32 select HAVE_DEBUG_STACKOVERFLOW
33 select OR1K_PIC
34 select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
35 select ARCH_USE_QUEUED_RWLOCKS
36 select OMPIC if SMP
37 select PCI_DOMAINS_GENERIC if PCI
38 select PCI_MSI if PCI
39 select ARCH_WANT_FRAME_POINTERS
40 select GENERIC_IRQ_MULTI_HANDLER
41 select MMU_GATHER_NO_RANGE if MMU
42 select TRACE_IRQFLAGS_SUPPORT
84 Select this if your implementation features write through data caches.
86 caches at relevant times. Most OpenRISC implementations support write-
101 Select this if your implementation has the Class II instruction l.ff1
107 Select this if your implementation has the Class II instruction l.fl1
113 Select this if your implementation has a hardware multiply instruction
119 Select this if your implementation has a hardware divide instruction
122 bool "Have instruction l.cmov for conditional move"
129 Select this if your implementation has support for the Class II
142 Select this if your implementation has support for the Class II
155 Select this if your implementation has support for the Class II
168 Select this if your implementation has support for the Class II
176 int "Maximum number of CPUs (2-32)"
182 bool "Symmetric Multi-Processing support"
222 supply some command-line options at build time by entering them