Lines Matching +full:pcie +full:- +full:mem
17 #include <asm/octeon/cvmx-npei-defs.h>
18 #include <asm/octeon/cvmx-pciercx-defs.h>
19 #include <asm/octeon/cvmx-pescx-defs.h>
20 #include <asm/octeon/cvmx-pexp-defs.h>
21 #include <asm/octeon/cvmx-pemx-defs.h>
22 #include <asm/octeon/cvmx-dpi-defs.h>
23 #include <asm/octeon/cvmx-sli-defs.h>
24 #include <asm/octeon/cvmx-sriox-defs.h>
25 #include <asm/octeon/cvmx-helper-errata.h>
26 #include <asm/octeon/pci-octeon.h>
46 uint64_t did:5; /* PCIe DID = 3 */
47 uint64_t subdid:3; /* PCIe SubDID = 1 */
50 uint64_t port:2; /* PCIe port 0,1 */
77 uint64_t did:5; /* PCIe DID = 3 */
78 uint64_t subdid:3; /* PCIe SubDID = 2 */
81 uint64_t port:2; /* PCIe port 0,1 */
82 uint64_t address:32; /* PCIe IO address */
88 uint64_t did:5; /* PCIe DID = 3 */
89 uint64_t subdid:3; /* PCIe SubDID = 3-6 */
91 uint64_t address:36; /* PCIe Mem address */
92 } mem; member
98 * Return the Core virtual base address for PCIe IO access. IOs are
101 * @pcie_port: PCIe port the IO is for
122 * @pcie_port: PCIe port the IO is for
132 * Return the Core virtual base address for PCIe MEM access. Memory is
135 * @pcie_port: PCIe port the IO is for
143 pcie_addr.mem.upper = 0; in cvmx_pcie_get_mem_base_address()
144 pcie_addr.mem.io = 1; in cvmx_pcie_get_mem_base_address()
145 pcie_addr.mem.did = 3; in cvmx_pcie_get_mem_base_address()
146 pcie_addr.mem.subdid = 3 + pcie_port; in cvmx_pcie_get_mem_base_address()
151 * Size of the Mem address region returned at address
154 * @pcie_port: PCIe port the IO is for
156 * Returns Size of the Mem window
164 * Read a PCIe config space register indirectly. This is used for
167 * @pcie_port: PCIe port to read from
192 * Write a PCIe config space register indirectly. This is used for
195 * @pcie_port: PCIe port to write to
218 * Build a PCIe config space request address for a device
220 * @pcie_port: PCIe port to access
257 * @pcie_port: PCIe port the device is on
279 * @pcie_port: PCIe port the device is on
301 * @pcie_port: PCIe port the device is on
323 * @pcie_port: PCIe port the device is on
342 * @pcie_port: PCIe port the device is on
361 * @pcie_port: PCIe port the device is on
380 * @pcie_port: PCIe port to initialize
397 /* Max Payload Size (PCIE*_CFG030[MPS]) */ in __cvmx_pcie_rc_initialize_config_space()
398 /* Max Read Request Size (PCIE*_CFG030[MRRS]) */ in __cvmx_pcie_rc_initialize_config_space()
399 /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */ in __cvmx_pcie_rc_initialize_config_space()
400 /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */ in __cvmx_pcie_rc_initialize_config_space()
419 /* Non-fatal error reporting enable. */ in __cvmx_pcie_rc_initialize_config_space()
432 * PCIE*_CFG030[MPS]. Max Read Request Size in __cvmx_pcie_rc_initialize_config_space()
434 * PCIE*_CFG030[MRRS] in __cvmx_pcie_rc_initialize_config_space()
450 * PCIE*_CFG030[MPS]. Max Read Request Size in __cvmx_pcie_rc_initialize_config_space()
452 * PCIE*_CFG030[MRRS]. in __cvmx_pcie_rc_initialize_config_space()
468 /* ECRC Generation (PCIE*_CFG070[GE,CE]) */ in __cvmx_pcie_rc_initialize_config_space()
475 * Access Enables (PCIE*_CFG001[MSAE,ME]) in __cvmx_pcie_rc_initialize_config_space()
477 * Interrupt Disable (PCIE*_CFG001[I_DIS]) in __cvmx_pcie_rc_initialize_config_space()
478 * System Error Message Enable (PCIE*_CFG001[SEE]) in __cvmx_pcie_rc_initialize_config_space()
488 /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */ in __cvmx_pcie_rc_initialize_config_space()
494 /* Active State Power Management (PCIE*_CFG032[ASLPC]) */ in __cvmx_pcie_rc_initialize_config_space()
500 * Link Width Mode (PCIERCn_CFG452[LME]) - Set during in __cvmx_pcie_rc_initialize_config_space()
516 * Memory-mapped I/O BAR (PCIERCn_CFG008) in __cvmx_pcie_rc_initialize_config_space()
517 * Most applications should disable the memory-mapped I/O BAR by in __cvmx_pcie_rc_initialize_config_space()
550 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
560 pciercx_cfg075.s.nfere = 1; /* Non-fatal error reporting enable. */ in __cvmx_pcie_rc_initialize_config_space()
569 pciercx_cfg034.s.hpint_en = 1; /* Hot-plug interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
576 * Initialize a host mode PCIe gen 1 link. This function takes a PCIe
580 * @pcie_port: PCIe port to initialize
636 if (cvmx_get_cycle() - start_cycle > 2 * octeon_get_clock_rate()) { in __cvmx_pcie_rc_initialize_link_gen1()
637 cvmx_dprintf("PCIe: Port %d link timeout\n", pcie_port); in __cvmx_pcie_rc_initialize_link_gen1()
638 return -1; in __cvmx_pcie_rc_initialize_link_gen1()
648 * Update the Replay Time Limit. Empirically, some PCIe in __cvmx_pcie_rc_initialize_link_gen1()
653 * from the PCIe spec table 3-4. in __cvmx_pcie_rc_initialize_link_gen1()
678 pmas->cn68xx.ba++; in __cvmx_increment_ba()
680 pmas->s.ba++; in __cvmx_increment_ba()
684 * Initialize a PCIe gen 1 port for use in host(RC) mode. It doesn't
687 * @pcie_port: PCIe port to initialize
714 cvmx_dprintf("PCIe: Port %d in endpoint mode\n", pcie_port); in __cvmx_pcie_rc_initialize_gen1()
715 return -1; in __cvmx_pcie_rc_initialize_gen1()
725 cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called on port1, but port1 is disabled\n"); in __cvmx_pcie_rc_initialize_gen1()
726 return -1; in __cvmx_pcie_rc_initialize_gen1()
731 * PCIe switch arbitration mode. '0' == fixed priority NPEI, in __cvmx_pcie_rc_initialize_gen1()
747 /* Bring the PCIe out of reset */ in __cvmx_pcie_rc_initialize_gen1()
748 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) { in __cvmx_pcie_rc_initialize_gen1()
750 * The EBH5200 board swapped the PCIe reset lines on in __cvmx_pcie_rc_initialize_gen1()
752 * both PCIe ports out of reset at the same time in __cvmx_pcie_rc_initialize_gen1()
759 * After a chip reset the PCIe will also be in in __cvmx_pcie_rc_initialize_gen1()
762 * PCIe reset. in __cvmx_pcie_rc_initialize_gen1()
771 /* Wait until pcie resets the ports. */ in __cvmx_pcie_rc_initialize_gen1()
783 * The normal case: The PCIe ports are completely in __cvmx_pcie_rc_initialize_gen1()
792 * After a chip reset the PCIe will also be in in __cvmx_pcie_rc_initialize_gen1()
794 * to init it again without a proper PCIe reset. in __cvmx_pcie_rc_initialize_gen1()
803 /* Wait until pcie resets the ports. */ in __cvmx_pcie_rc_initialize_gen1()
818 * Wait for PCIe reset to complete. Due to errata PCIE-700, we in __cvmx_pcie_rc_initialize_gen1()
838 cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n", pcie_port); in __cvmx_pcie_rc_initialize_gen1()
839 return -1; in __cvmx_pcie_rc_initialize_gen1()
844 * Check and make sure PCIe came out of reset. If it doesn't in __cvmx_pcie_rc_initialize_gen1()
850 cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n", pcie_port); in __cvmx_pcie_rc_initialize_gen1()
851 return -1; in __cvmx_pcie_rc_initialize_gen1()
856 * interface. This is an attempt to catch PCIE-813 on pass 1 in __cvmx_pcie_rc_initialize_gen1()
861 cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this port isn't hooked up, skipping.\n", in __cvmx_pcie_rc_initialize_gen1()
863 return -1; in __cvmx_pcie_rc_initialize_gen1()
869 cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n", in __cvmx_pcie_rc_initialize_gen1()
877 cvmx_dprintf("PCIe: Failed to initialize port %d, probably the slot is empty\n", in __cvmx_pcie_rc_initialize_gen1()
879 return -1; in __cvmx_pcie_rc_initialize_gen1()
888 /* Setup Mem access SubDIDs */ in __cvmx_pcie_rc_initialize_gen1()
892 mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */ in __cvmx_pcie_rc_initialize_gen1()
893 mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */ in __cvmx_pcie_rc_initialize_gen1()
898 mem_access_subid.s.ba = 0; /* PCIe Address Bits <63:34>. */ in __cvmx_pcie_rc_initialize_gen1()
901 * Setup mem access 12-15 for port 0, 16-19 for port 1, in __cvmx_pcie_rc_initialize_gen1()
912 * addresses to the PCIe busses. in __cvmx_pcie_rc_initialize_gen1()
915 cvmx_write_csr(CVMX_PESCX_P2P_BARX_START(i, pcie_port), -1); in __cvmx_pcie_rc_initialize_gen1()
916 cvmx_write_csr(CVMX_PESCX_P2P_BARX_END(i, pcie_port), -1); in __cvmx_pcie_rc_initialize_gen1()
919 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */ in __cvmx_pcie_rc_initialize_gen1()
933 /* Big endian swizzle for 32-bit PEXP_NCB register. */ in __cvmx_pcie_rc_initialize_gen1()
948 * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take in __cvmx_pcie_rc_initialize_gen1()
959 * - PTLP_RO,CTLP_RO should normally be set (except for debug). in __cvmx_pcie_rc_initialize_gen1()
960 * - WAIT_COM=0 will likely work for all applications. in __cvmx_pcie_rc_initialize_gen1()
991 * PCIe port resets. This code detects this fault and corrects in __cvmx_pcie_rc_initialize_gen1()
993 * reset is then performed. See PCIE-13340 in __cvmx_pcie_rc_initialize_gen1()
1017 while (i--) { in __cvmx_pcie_rc_initialize_gen1()
1051 …cvmx_dprintf("PCIe: Port %d aligning TLP counters as workaround to maintain ordering\n", pcie_port… in __cvmx_pcie_rc_initialize_gen1()
1058 * The EBH5200 board swapped the PCIe reset in __cvmx_pcie_rc_initialize_gen1()
1065 if ((cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) && in __cvmx_pcie_rc_initialize_gen1()
1075 cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port, pciercx_cfg032.s.nlw); in __cvmx_pcie_rc_initialize_gen1()
1081 * Initialize a host mode PCIe gen 2 link. This function takes a PCIe
1085 * @pcie_port: PCIe port to initialize
1104 if (cvmx_get_cycle() - start_cycle > octeon_get_clock_rate()) in __cvmx_pcie_rc_initialize_link_gen2()
1105 return -1; in __cvmx_pcie_rc_initialize_link_gen2()
1111 * Update the Replay Time Limit. Empirically, some PCIe in __cvmx_pcie_rc_initialize_link_gen2()
1116 * from the PCIe spec table 3-4 in __cvmx_pcie_rc_initialize_link_gen2()
1140 * Initialize a PCIe gen 2 port for use in host(RC) mode. It doesn't enumerate
1143 * @pcie_port: PCIe port to initialize
1176 pr_notice("PCIe: Port %d is disabled, skipping.\n", pcie_port); in __cvmx_pcie_rc_initialize_gen2()
1177 return -1; in __cvmx_pcie_rc_initialize_gen2()
1185 pr_notice("PCIe: Port %d is SRIO, skipping.\n", pcie_port); in __cvmx_pcie_rc_initialize_gen2()
1186 return -1; in __cvmx_pcie_rc_initialize_gen2()
1188 pr_notice("PCIe: Port %d is SGMII, skipping.\n", pcie_port); in __cvmx_pcie_rc_initialize_gen2()
1189 return -1; in __cvmx_pcie_rc_initialize_gen2()
1191 pr_notice("PCIe: Port %d is XAUI, skipping.\n", pcie_port); in __cvmx_pcie_rc_initialize_gen2()
1192 return -1; in __cvmx_pcie_rc_initialize_gen2()
1193 case 0x0: /* PCIE gen2 */ in __cvmx_pcie_rc_initialize_gen2()
1194 case 0x8: /* PCIE gen2 (alias) */ in __cvmx_pcie_rc_initialize_gen2()
1195 case 0x2: /* PCIE gen1 */ in __cvmx_pcie_rc_initialize_gen2()
1196 case 0xa: /* PCIE gen1 (alias) */ in __cvmx_pcie_rc_initialize_gen2()
1199 pr_notice("PCIe: Port %d is unknown, skipping.\n", pcie_port); in __cvmx_pcie_rc_initialize_gen2()
1200 return -1; in __cvmx_pcie_rc_initialize_gen2()
1205 pr_notice("PCIe: Port %d is SRIO, skipping.\n", pcie_port); in __cvmx_pcie_rc_initialize_gen2()
1206 return -1; in __cvmx_pcie_rc_initialize_gen2()
1212 /* This code is so that the PCIe analyzer is able to see 63XX traffic */ in __cvmx_pcie_rc_initialize_gen2()
1213 pr_notice("PCIE : init for pcie analyzer.\n"); in __cvmx_pcie_rc_initialize_gen2()
1217 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86); in __cvmx_pcie_rc_initialize_gen2()
1220 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86); in __cvmx_pcie_rc_initialize_gen2()
1223 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86); in __cvmx_pcie_rc_initialize_gen2()
1226 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86); in __cvmx_pcie_rc_initialize_gen2()
1233 pr_notice("PCIe: Port %d in endpoint mode.\n", pcie_port); in __cvmx_pcie_rc_initialize_gen2()
1234 return -1; in __cvmx_pcie_rc_initialize_gen2()
1237 /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be programmed */ in __cvmx_pcie_rc_initialize_gen2()
1255 /* Bring the PCIe out of reset */ in __cvmx_pcie_rc_initialize_gen2()
1261 * After a chip reset the PCIe will also be in reset. If it in __cvmx_pcie_rc_initialize_gen2()
1263 * without a proper PCIe reset in __cvmx_pcie_rc_initialize_gen2()
1272 /* Wait until pcie resets the ports. */ in __cvmx_pcie_rc_initialize_gen2()
1285 /* Wait for PCIe reset to complete */ in __cvmx_pcie_rc_initialize_gen2()
1289 * Check and make sure PCIe came out of reset. If it doesn't in __cvmx_pcie_rc_initialize_gen2()
1294 pr_notice("PCIe: Port %d stuck in reset, skipping.\n", pcie_port); in __cvmx_pcie_rc_initialize_gen2()
1295 return -1; in __cvmx_pcie_rc_initialize_gen2()
1301 pr_notice("PCIe: BIST FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status.u64)); in __cvmx_pcie_rc_initialize_gen2()
1303 /* Errata PCIE-14766 may cause the lower 6 bits to be randomly set on CN63XXp1 */ in __cvmx_pcie_rc_initialize_gen2()
1307 …pr_notice("PCIe: BIST2 FAILED for port %d (0x%016llx)\n", pcie_port, CAST64(pemx_bist_status2.u64)… in __cvmx_pcie_rc_initialize_gen2()
1329 pr_notice("PCIe: Link timeout on port %d, probably the slot is empty\n", pcie_port); in __cvmx_pcie_rc_initialize_gen2()
1330 return -1; in __cvmx_pcie_rc_initialize_gen2()
1340 /* Setup Mem access SubDIDs */ in __cvmx_pcie_rc_initialize_gen2()
1344 mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */ in __cvmx_pcie_rc_initialize_gen2()
1345 mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */ in __cvmx_pcie_rc_initialize_gen2()
1348 /* PCIe Address Bits <63:34>. */ in __cvmx_pcie_rc_initialize_gen2()
1355 * Setup mem access 12-15 for port 0, 16-19 for port 1, in __cvmx_pcie_rc_initialize_gen2()
1367 * addresses to the PCIe busses. in __cvmx_pcie_rc_initialize_gen2()
1370 cvmx_write_csr(CVMX_PEMX_P2P_BARX_START(i, pcie_port), -1); in __cvmx_pcie_rc_initialize_gen2()
1371 cvmx_write_csr(CVMX_PEMX_P2P_BARX_END(i, pcie_port), -1); in __cvmx_pcie_rc_initialize_gen2()
1374 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */ in __cvmx_pcie_rc_initialize_gen2()
1378 * Set Octeon's BAR2 to decode 0-2^41. Bar0 and Bar1 take in __cvmx_pcie_rc_initialize_gen2()
1388 * - PTLP_RO,CTLP_RO should normally be set (except for debug). in __cvmx_pcie_rc_initialize_gen2()
1389 * - WAIT_COM=0 will likely work for all applications. in __cvmx_pcie_rc_initialize_gen2()
1430 …pr_notice("PCIe: Port %d link active, %d lanes, speed gen%d\n", pcie_port, pciercx_cfg032.s.nlw, p… in __cvmx_pcie_rc_initialize_gen2()
1436 * Initialize a PCIe port for use in host(RC) mode. It doesn't enumerate the bus.
1438 * @pcie_port: PCIe port to initialize
1452 /* Above was cvmx-pcie.c, below original pcie.c */
1468 * The EBH5600 board with the PCI to PCIe bridge mistakenly in octeon_pcie_pcibios_map_irq()
1474 dev->bus && dev->bus->parent) { in octeon_pcie_pcibios_map_irq()
1479 while (dev->bus && dev->bus->parent) in octeon_pcie_pcibios_map_irq()
1480 dev = to_pci_dev(dev->bus->bridge); in octeon_pcie_pcibios_map_irq()
1486 if ((dev->bus->number == 1) && in octeon_pcie_pcibios_map_irq()
1487 (dev->vendor == 0x10b5) && (dev->device == 0x8114)) { in octeon_pcie_pcibios_map_irq()
1492 pin = ((pin - 3) & 3) + 1; in octeon_pcie_pcibios_map_irq()
1496 * The -1 is because pin starts with one, not zero. It might in octeon_pcie_pcibios_map_irq()
1500 return pin - 1 + OCTEON_IRQ_PCI_INT0; in octeon_pcie_pcibios_map_irq()
1543 int bus_number = bus->number; in octeon_pcie_read_config()
1555 if (bus->parent == NULL) { in octeon_pcie_read_config()
1574 * PCIe only has a single device connected to Octeon. It is in octeon_pcie_read_config()
1578 if ((bus->parent == NULL) && (devfn >> 3 != 0)) in octeon_pcie_read_config()
1583 * CN55XX, and CN54XX errata with PCIe config reads from non in octeon_pcie_read_config()
1584 * existent devices. These chips will hang the PCIe link if a in octeon_pcie_read_config()
1591 * PCI-X slots. We need a new special checks to make in octeon_pcie_read_config()
1592 * sure we only probe valid stuff. The PCIe->PCI-X in octeon_pcie_read_config()
1594 * 0-1 in octeon_pcie_read_config()
1596 if ((bus->parent == NULL) && (devfn >= 2)) in octeon_pcie_read_config()
1599 * The PCI-X slots are device ID 2,3. Choose one of in octeon_pcie_read_config()
1629 the required checks for running a Nitrox CN16XX-NHBX in the in octeon_pcie_read_config()
1630 slot of the EBH5600. This card has a PLX PCIe bridge with in octeon_pcie_read_config()
1652 * Shorten the DID timeout so bus errors for PCIe in octeon_pcie_read_config()
1656 * errors happens, the PCIe port is dead. in octeon_pcie_read_config()
1693 pr_err(" pcie cfg_read retries failed. retry_cnt=%d\n", in octeon_pcie_read_config()
1734 int bus_number = bus->number; in octeon_pcie_write_config()
1738 if ((bus->parent == NULL) && (enable_pcie_bus_num_war[pcie_port])) in octeon_pcie_write_config()
1789 .name = "Octeon PCIe0 MEM",
1810 .name = "Octeon PCIe1 MEM",
1831 .name = "Virtual PCIe MEM",
1836 .name = "Virtual PCIe IO",
1856 * Initialize the Octeon PCIe controllers
1868 /* These chips don't have PCIe */ in octeon_pcie_setup()
1872 /* No PCIe simulation */ in octeon_pcie_setup()
1880 /* Point pcibios_map_irq() to the PCIe version of it */ in octeon_pcie_setup()
1884 * PCIe I/O range. It is based on port 0 but includes up until in octeon_pcie_setup()
1890 cvmx_pcie_get_io_base_address(1) - in octeon_pcie_setup()
1891 cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1; in octeon_pcie_setup()
1894 * Create a dummy PCIe controller to swallow up bus 0. IDT bridges in octeon_pcie_setup()
1896 * PCIe controller that the kernel will give bus 0. This allows in octeon_pcie_setup()
1899 octeon_dummy_controller.io_map_base = -1; in octeon_pcie_setup()
1900 octeon_dummy_controller.mem_resource->start = (1ull<<48); in octeon_pcie_setup()
1901 octeon_dummy_controller.mem_resource->end = (1ull<<48); in octeon_pcie_setup()
1917 pr_notice("PCIe: Initializing port 0\n"); in octeon_pcie_setup()
1918 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */ in octeon_pcie_setup()
1942 * translates to 4GB-256MB, which is the same in octeon_pcie_setup()
1945 octeon_pcie0_controller.mem_resource->start = in octeon_pcie_setup()
1947 (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20); in octeon_pcie_setup()
1948 octeon_pcie0_controller.mem_resource->end = in octeon_pcie_setup()
1950 cvmx_pcie_get_mem_size(0) - 1; in octeon_pcie_setup()
1953 * filtering in the PCI-X to PCI bridge. in octeon_pcie_setup()
1955 octeon_pcie0_controller.io_resource->start = 4 << 10; in octeon_pcie_setup()
1956 octeon_pcie0_controller.io_resource->end = in octeon_pcie_setup()
1957 cvmx_pcie_get_io_size(0) - 1; in octeon_pcie_setup()
1965 pr_notice("PCIe: Port 0 in endpoint mode, skipping.\n"); in octeon_pcie_setup()
1966 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */ in octeon_pcie_setup()
1990 pr_notice("PCIe: Initializing port 1\n"); in octeon_pcie_setup()
1991 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */ in octeon_pcie_setup()
2007 * To calculate the address for accessing the 2nd PCIe device, in octeon_pcie_setup()
2011 * only once based on first PCIe. Also changing 'io_map_base' in octeon_pcie_setup()
2019 cvmx_pcie_get_io_base_address(1) - in octeon_pcie_setup()
2024 * support. This normally translates to 4GB-256MB, in octeon_pcie_setup()
2027 octeon_pcie1_controller.mem_resource->start = in octeon_pcie_setup()
2028 cvmx_pcie_get_mem_base_address(1) + (4ul << 30) - in octeon_pcie_setup()
2030 octeon_pcie1_controller.mem_resource->end = in octeon_pcie_setup()
2032 cvmx_pcie_get_mem_size(1) - 1; in octeon_pcie_setup()
2035 * in the PCI-X to PCI bridge. in octeon_pcie_setup()
2037 octeon_pcie1_controller.io_resource->start = in octeon_pcie_setup()
2038 cvmx_pcie_get_io_base_address(1) - in octeon_pcie_setup()
2040 octeon_pcie1_controller.io_resource->end = in octeon_pcie_setup()
2041 octeon_pcie1_controller.io_resource->start + in octeon_pcie_setup()
2042 cvmx_pcie_get_io_size(1) - 1; in octeon_pcie_setup()
2050 pr_notice("PCIe: Port 1 not in root complex mode, skipping.\n"); in octeon_pcie_setup()
2051 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */ in octeon_pcie_setup()
2060 * CN63XX pass 1_x/2.0 errata PCIe-15205 requires setting all in octeon_pcie_setup()
2062 * all of PCIe Macs SLI_CTL_PORT*[INT*_MAP] to different value in octeon_pcie_setup()