75 	 * separate caches).  in r4k_op_needs_ipi()
387 		 * These caches are inclusive caches, that is, if something  in local_r4k___flush_cache_all()
389 		 * in one of the primary caches.  in local_r4k___flush_cache_all()
468  * whole caches when vma is executable.
508 	 * only flush the primary caches but R1x000 behave sane ...  in local_r4k_flush_cache_mm()
510 	 * caches, so we can bail out early.  in local_r4k_flush_cache_mm()
770 	 * Either no secondary cache or the available caches don't have the  in r4k_dma_cache_wback_inv()
771 	 * subset property so we have to flush the primary caches  in r4k_dma_cache_wback_inv()
874 	 * Aliases only affect the primary caches so don't bother with  in local_r4k_flush_kernel_vmap_range_index()
875 	 * S-caches or T-caches.  in local_r4k_flush_kernel_vmap_range_index()
887 	 * Aliases only affect the primary caches so don't bother with  in local_r4k_flush_kernel_vmap_range()
888 	 * S-caches or T-caches.  in local_r4k_flush_kernel_vmap_range()
1004 	case CPU_R4600:			/* QED style two way caches? */  in probe_pcache()
1170 			panic("Don't know how to probe P-caches on this cpu.");  in probe_pcache()
1246 	 * R1x000 P-caches are odd in a positive way.  They're 32kB 2-way  in probe_pcache()
1300 	/* Physically indexed caches don't suffer from virtual aliasing */  in probe_pcache()
1305 	 * In systems with CM the icache fills from L2 or closer caches, and  in probe_pcache()
1722 	 * Some MIPS32 and MIPS64 processors have physically indexed caches.  in r4k_cache_init()
1762 	 * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether  in r4k_cache_init()
1763 	 * or not to flush caches.  in r4k_cache_init()