Lines Matching +full:4 +full:- +full:way
22 #include <linux/dma-map-ops.h> /* for dma_default_coherent */
29 #include <asm/cpu-features.h>
30 #include <asm/cpu-type.h>
38 #include <asm/mips-cps.h>
43 * R4K_HIT - Virtual user or kernel address based cache operations. The
46 * R4K_INDEX - Index based cache operations.
53 * r4k_op_needs_ipi() - Decide if a cache op needs to be done on every core.
68 /* The MIPS Coherence Manager (CM) globalizes address-based cache ops */ in r4k_op_needs_ipi()
74 * be needed, but only if there are foreign CPUs (non-siblings with in r4k_op_needs_ipi()
388 * is not cached in the S-cache, we know it also won't be in local_r4k___flush_cache_all()
417 * has_valid_asid() - Determine if an mm already has an ASID.
427 * Must be called in non-preemptive context.
473 int exec = vma->vm_flags & VM_EXEC; in local_r4k_flush_cache_range()
475 if (!has_valid_asid(vma->vm_mm, R4K_INDEX)) in local_r4k_flush_cache_range()
493 int exec = vma->vm_flags & VM_EXEC; in r4k_flush_cache_range()
509 * R4000SC and R4400SC indexed S-cache ops also invalidate primary in local_r4k_flush_cache_mm()
540 struct vm_area_struct *vma = fcp_args->vma; in local_r4k_flush_cache_page()
541 unsigned long addr = fcp_args->addr; in local_r4k_flush_cache_page()
542 struct page *page = pfn_to_page(fcp_args->pfn); in local_r4k_flush_cache_page()
543 int exec = vma->vm_flags & VM_EXEC; in local_r4k_flush_cache_page()
544 struct mm_struct *mm = vma->vm_mm; in local_r4k_flush_cache_page()
568 if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID)) in local_r4k_flush_cache_page()
593 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) { in local_r4k_flush_cache_page()
648 (type & R4K_INDEX && end - start >= dcache_size)) { in __local_r4k_flush_icache_range()
660 (type & R4K_INDEX && end - start > icache_size)) in __local_r4k_flush_icache_range()
693 unsigned long start = fir_args->start; in local_r4k_flush_icache_range_ipi()
694 unsigned long end = fir_args->end; in local_r4k_flush_icache_range_ipi()
695 unsigned int type = fir_args->type; in local_r4k_flush_icache_range_ipi()
696 bool user = fir_args->user; in local_r4k_flush_icache_range_ipi()
719 * If address-based cache ops don't require an SMP call, then in __r4k_flush_icache_range()
722 size = end - start; in __r4k_flush_icache_range()
773 * If we would need IPI to perform an INDEX-type operation, then in r4k_dma_cache_wback_inv()
774 * we have to use the HIT-type alternative as IPI cannot be used in r4k_dma_cache_wback_inv()
794 addr0 &= ~(linesz - 1); in prefetch_cache_inv()
795 addr1 = (addr0 + size - 1) & ~(linesz - 1); in prefetch_cache_inv()
809 addr1 -= linesz; in prefetch_cache_inv()
875 * S-caches or T-caches. in local_r4k_flush_kernel_vmap_range_index()
883 unsigned long vaddr = vmra->vaddr; in local_r4k_flush_kernel_vmap_range()
884 int size = vmra->size; in local_r4k_flush_kernel_vmap_range()
888 * S-caches or T-caches. in local_r4k_flush_kernel_vmap_range()
943 unsigned int imp = c->processor_id & PRID_IMP_MASK; in alias_74k_erratum()
944 unsigned int rev = c->processor_id & PRID_REV_MASK; in alias_74k_erratum()
954 * address hit during a D-cache look-up. in alias_74k_erratum()
958 if (rev <= PRID_REV_ENCODE_332(2, 4, 0)) in alias_74k_erratum()
960 if (rev == PRID_REV_ENCODE_332(2, 4, 0)) in alias_74k_erratum()
988 static char *way_string[] = { NULL, "direct mapped", "2-way",
989 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way",
990 "9-way", "10-way", "11-way", "12-way",
991 "13-way", "14-way", "15-way", "16-way",
1004 case CPU_R4600: /* QED style two way caches? */ in probe_pcache()
1009 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); in probe_pcache()
1010 c->icache.ways = 2; in probe_pcache()
1011 c->icache.waybit = __ffs(icache_size/2); in probe_pcache()
1014 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1015 c->dcache.ways = 2; in probe_pcache()
1016 c->dcache.waybit= __ffs(dcache_size/2); in probe_pcache()
1018 c->options |= MIPS_CPU_CACHE_CDEX_P; in probe_pcache()
1023 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); in probe_pcache()
1024 c->icache.ways = 2; in probe_pcache()
1025 c->icache.waybit= 0; in probe_pcache()
1028 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1029 c->dcache.ways = 2; in probe_pcache()
1030 c->dcache.waybit = 0; in probe_pcache()
1032 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; in probe_pcache()
1037 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); in probe_pcache()
1038 c->icache.ways = 4; in probe_pcache()
1039 c->icache.waybit= 0; in probe_pcache()
1042 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1043 c->dcache.ways = 4; in probe_pcache()
1044 c->dcache.waybit = 0; in probe_pcache()
1046 c->options |= MIPS_CPU_CACHE_CDEX_P; in probe_pcache()
1047 c->options |= MIPS_CPU_PREFETCH; in probe_pcache()
1058 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); in probe_pcache()
1059 c->icache.ways = 1; in probe_pcache()
1060 c->icache.waybit = 0; /* doesn't matter */ in probe_pcache()
1063 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1064 c->dcache.ways = 1; in probe_pcache()
1065 c->dcache.waybit = 0; /* does not matter */ in probe_pcache()
1067 c->options |= MIPS_CPU_CACHE_CDEX_P; in probe_pcache()
1075 c->icache.linesz = 64; in probe_pcache()
1076 c->icache.ways = 2; in probe_pcache()
1077 c->icache.waybit = 0; in probe_pcache()
1080 c->dcache.linesz = 32; in probe_pcache()
1081 c->dcache.ways = 2; in probe_pcache()
1082 c->dcache.waybit = 0; in probe_pcache()
1084 c->options |= MIPS_CPU_PREFETCH; in probe_pcache()
1091 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); in probe_pcache()
1092 c->icache.ways = 4; in probe_pcache()
1093 c->icache.waybit = __ffs(icache_size / c->icache.ways); in probe_pcache()
1096 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1097 c->dcache.ways = 4; in probe_pcache()
1098 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways); in probe_pcache()
1100 c->options |= MIPS_CPU_CACHE_CDEX_P; in probe_pcache()
1101 c->options |= MIPS_CPU_PREFETCH; in probe_pcache()
1106 c->icache.linesz = 16 << ((config & CONF_IB) >> 5); in probe_pcache()
1108 c->icache.ways = 4; in probe_pcache()
1110 c->icache.ways = 2; in probe_pcache()
1111 c->icache.waybit = 0; in probe_pcache()
1114 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1116 c->dcache.ways = 4; in probe_pcache()
1118 c->dcache.ways = 2; in probe_pcache()
1119 c->dcache.waybit = 0; in probe_pcache()
1126 c->icache.linesz = 2 << lsize; in probe_pcache()
1128 c->icache.linesz = 0; in probe_pcache()
1129 c->icache.sets = 64 << ((config1 >> 22) & 7); in probe_pcache()
1130 c->icache.ways = 1 + ((config1 >> 16) & 7); in probe_pcache()
1131 icache_size = c->icache.sets * in probe_pcache()
1132 c->icache.ways * in probe_pcache()
1133 c->icache.linesz; in probe_pcache()
1134 c->icache.waybit = 0; in probe_pcache()
1138 c->dcache.linesz = 2 << lsize; in probe_pcache()
1140 c->dcache.linesz = 0; in probe_pcache()
1141 c->dcache.sets = 64 << ((config1 >> 13) & 7); in probe_pcache()
1142 c->dcache.ways = 1 + ((config1 >> 7) & 7); in probe_pcache()
1143 dcache_size = c->dcache.sets * in probe_pcache()
1144 c->dcache.ways * in probe_pcache()
1145 c->dcache.linesz; in probe_pcache()
1146 c->dcache.waybit = 0; in probe_pcache()
1147 if ((c->processor_id & (PRID_IMP_MASK | PRID_REV_MASK)) >= in probe_pcache()
1149 (c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R) in probe_pcache()
1150 c->options |= MIPS_CPU_PREFETCH; in probe_pcache()
1155 c->icache.linesz = 128; in probe_pcache()
1156 c->icache.sets = 16; in probe_pcache()
1157 c->icache.ways = 8; in probe_pcache()
1158 c->icache.flags |= MIPS_CACHE_VTAG; in probe_pcache()
1159 icache_size = c->icache.sets * c->icache.ways * c->icache.linesz; in probe_pcache()
1161 c->dcache.linesz = 128; in probe_pcache()
1162 c->dcache.ways = 8; in probe_pcache()
1163 c->dcache.sets = 8; in probe_pcache()
1164 dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_pcache()
1165 c->options |= MIPS_CPU_PREFETCH; in probe_pcache()
1170 panic("Don't know how to probe P-caches on this cpu."); in probe_pcache()
1174 * So let's probe the I-cache ... in probe_pcache()
1184 c->icache.linesz = lsize ? 2 << lsize : 0; in probe_pcache()
1186 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7); in probe_pcache()
1187 c->icache.ways = 1 + ((config1 >> 16) & 7); in probe_pcache()
1189 icache_size = c->icache.sets * in probe_pcache()
1190 c->icache.ways * in probe_pcache()
1191 c->icache.linesz; in probe_pcache()
1192 c->icache.waybit = __ffs(icache_size/c->icache.ways); in probe_pcache()
1195 c->icache.flags |= MIPS_CACHE_VTAG; in probe_pcache()
1200 c->dcache.flags = 0; in probe_pcache()
1208 c->dcache.linesz = lsize ? 2 << lsize : 0; in probe_pcache()
1210 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7); in probe_pcache()
1211 c->dcache.ways = 1 + ((config1 >> 7) & 7); in probe_pcache()
1213 dcache_size = c->dcache.sets * in probe_pcache()
1214 c->dcache.ways * in probe_pcache()
1215 c->dcache.linesz; in probe_pcache()
1216 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways); in probe_pcache()
1218 c->options |= MIPS_CPU_PREFETCH; in probe_pcache()
1232 !(config & CONF_SC) && c->icache.linesz != 16 && in probe_pcache()
1237 c->icache.waysize = icache_size / c->icache.ways; in probe_pcache()
1238 c->dcache.waysize = dcache_size / c->dcache.ways; in probe_pcache()
1240 c->icache.sets = c->icache.linesz ? in probe_pcache()
1241 icache_size / (c->icache.linesz * c->icache.ways) : 0; in probe_pcache()
1242 c->dcache.sets = c->dcache.linesz ? in probe_pcache()
1243 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0; in probe_pcache()
1246 * R1x000 P-caches are odd in a positive way. They're 32kB 2-way in probe_pcache()
1258 c->dcache.flags |= MIPS_CACHE_PINDEX; in probe_pcache()
1284 (c->icache.waysize > PAGE_SIZE)) in probe_pcache()
1285 c->icache.flags |= MIPS_CACHE_ALIASES; in probe_pcache()
1291 c->dcache.flags |= MIPS_CACHE_PINDEX; in probe_pcache()
1296 if (has_74k_erratum || c->dcache.waysize > PAGE_SIZE) in probe_pcache()
1297 c->dcache.flags |= MIPS_CACHE_ALIASES; in probe_pcache()
1301 if (c->dcache.flags & MIPS_CACHE_PINDEX) in probe_pcache()
1302 c->dcache.flags &= ~MIPS_CACHE_ALIASES; in probe_pcache()
1310 c->icache.flags |= MIPS_IC_SNOOPS_REMOTE; in probe_pcache()
1318 c->icache.flags |= MIPS_CACHE_VTAG; in probe_pcache()
1324 c->icache.flags |= MIPS_CACHE_IC_F_DC; in probe_pcache()
1328 c->icache.flags |= MIPS_CACHE_IC_F_DC; in probe_pcache()
1330 c->dcache.flags &= ~MIPS_CACHE_ALIASES; in probe_pcache()
1335 * LOONGSON2 has 4 way icache, but when using indexed cache op, in probe_pcache()
1336 * one op will act on all 4 ways in probe_pcache()
1338 c->icache.ways = 1; in probe_pcache()
1343 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", in probe_pcache()
1344 way_string[c->icache.ways], c->icache.linesz); in probe_pcache()
1347 dcache_size >> 10, way_string[c->dcache.ways], in probe_pcache()
1348 (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT", in probe_pcache()
1349 (c->dcache.flags & MIPS_CACHE_ALIASES) ? in probe_pcache()
1351 c->dcache.linesz); in probe_pcache()
1364 c->vcache.linesz = 2 << lsize; in probe_vcache()
1366 c->vcache.linesz = lsize; in probe_vcache()
1368 c->vcache.sets = 64 << ((config2 >> 24) & 15); in probe_vcache()
1369 c->vcache.ways = 1 + ((config2 >> 16) & 15); in probe_vcache()
1371 vcache_size = c->vcache.sets * c->vcache.ways * c->vcache.linesz; in probe_vcache()
1373 c->vcache.waybit = 0; in probe_vcache()
1374 c->vcache.waysize = vcache_size / c->vcache.ways; in probe_vcache()
1377 vcache_size >> 10, way_string[c->vcache.ways], c->vcache.linesz); in probe_vcache()
1396 begin &= ~((4 * 1024 * 1024) - 1); in probe_scache()
1397 end = begin + (4 * 1024 * 1024); in probe_scache()
1405 /* Fill each size-multiple cache line with a valid tag. */ in probe_scache()
1431 addr -= begin; in probe_scache()
1434 c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22); in probe_scache()
1435 c->scache.ways = 1; in probe_scache()
1436 c->scache.waybit = 0; /* does not matter */ in probe_scache()
1446 c->scache.linesz = 32; in loongson2_sc_init()
1447 c->scache.ways = 4; in loongson2_sc_init()
1448 c->scache.waybit = 0; in loongson2_sc_init()
1449 c->scache.waysize = scache_size / (c->scache.ways); in loongson2_sc_init()
1450 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); in loongson2_sc_init()
1452 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); in loongson2_sc_init()
1454 c->options |= MIPS_CPU_INCLUSIVE_CACHES; in loongson2_sc_init()
1463 lsize = (config2 >> 4) & 15; in loongson3_sc_init()
1465 c->scache.linesz = 2 << lsize; in loongson3_sc_init()
1467 c->scache.linesz = 0; in loongson3_sc_init()
1468 c->scache.sets = 64 << ((config2 >> 8) & 15); in loongson3_sc_init()
1469 c->scache.ways = 1 + (config2 & 15); in loongson3_sc_init()
1471 /* Loongson-3 has 4-Scache banks, while Loongson-2K have only 2 banks */ in loongson3_sc_init()
1472 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R) in loongson3_sc_init()
1473 c->scache.sets *= 2; in loongson3_sc_init()
1475 c->scache.sets *= 4; in loongson3_sc_init()
1477 scache_size = c->scache.sets * c->scache.ways * c->scache.linesz; in loongson3_sc_init()
1479 c->scache.waybit = 0; in loongson3_sc_init()
1480 c->scache.waysize = scache_size / c->scache.ways; in loongson3_sc_init()
1482 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); in loongson3_sc_init()
1484 c->options |= MIPS_CPU_INCLUSIVE_CACHES; in loongson3_sc_init()
1496 * processors don't have a S-cache that would be relevant to the in setup_scache()
1506 c->options |= MIPS_CPU_CACHE_CDEX_S; in setup_scache()
1514 c->scache.linesz = 64 << ((config >> 13) & 1); in setup_scache()
1515 c->scache.ways = 2; in setup_scache()
1516 c->scache.waybit= 0; in setup_scache()
1546 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 | in setup_scache()
1552 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz; in setup_scache()
1555 way_string[c->scache.ways], c->scache.linesz); in setup_scache()
1558 c->options |= MIPS_CPU_INCLUSIVE_CACHES; in setup_scache()
1562 if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT)) in setup_scache()
1574 c->scache.waysize = scache_size / c->scache.ways; in setup_scache()
1576 c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways); in setup_scache()
1579 scache_size >> 10, way_string[c->scache.ways], c->scache.linesz); in setup_scache()
1581 c->options |= MIPS_CPU_INCLUSIVE_CACHES; in setup_scache()
1631 static int cca = -1;
1669 * the write-only co_config.od bit and set it back to one on: in coherency_setup()
1726 if (c->dcache.linesz && cpu_has_dc_aliases) in r4k_cache_init()
1728 c->dcache.sets * c->dcache.linesz - 1, in r4k_cache_init()
1729 PAGE_SIZE - 1); in r4k_cache_init()
1731 shm_align_mask = PAGE_SIZE-1; in r4k_cache_init()
1771 * Per-CPU overrides in r4k_cache_init()
1781 if (c->scache.flags & MIPS_CACHE_NOT_PRESENT) in r4k_cache_init()
1796 /* Loongson-3 maintains cache coherency by hardware */ in r4k_cache_init()