Lines Matching +full:cpu +full:- +full:core
1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/cpu.h>
38 static u32 (*ipi_read_clear)(int cpu);
39 static void (*ipi_write_action)(int cpu, u32 action);
40 static void (*ipi_write_enable)(int cpu);
41 static void (*ipi_clear_buf)(int cpu);
42 static void (*ipi_write_buf)(int cpu, struct task_struct *idle);
44 /* send mail via Mail_Send register for 3A4000+ CPU */
45 static void csr_mail_send(uint64_t data, int cpu, int mailbox) in csr_mail_send() argument
52 val |= (cpu << CSR_MAIL_SEND_CPU_SHIFT); in csr_mail_send()
59 val |= (cpu << CSR_MAIL_SEND_CPU_SHIFT); in csr_mail_send()
64 static u32 csr_ipi_read_clear(int cpu) in csr_ipi_read_clear() argument
76 static void csr_ipi_write_action(int cpu, u32 action) in csr_ipi_write_action() argument
82 val |= (irq - 1); in csr_ipi_write_action()
83 val |= (cpu << CSR_IPI_SEND_CPU_SHIFT); in csr_ipi_write_action()
85 action &= ~BIT(irq - 1); in csr_ipi_write_action()
89 static void csr_ipi_write_enable(int cpu) in csr_ipi_write_enable() argument
94 static void csr_ipi_clear_buf(int cpu) in csr_ipi_clear_buf() argument
99 static void csr_ipi_write_buf(int cpu, struct task_struct *idle) in csr_ipi_write_buf() argument
103 /* startargs[] are initial PC, SP and GP for secondary CPU */ in csr_ipi_write_buf()
109 pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n", in csr_ipi_write_buf()
110 cpu, startargs[0], startargs[1], startargs[2]); in csr_ipi_write_buf()
112 csr_mail_send(startargs[3], cpu_logical_map(cpu), 3); in csr_ipi_write_buf()
113 csr_mail_send(startargs[2], cpu_logical_map(cpu), 2); in csr_ipi_write_buf()
114 csr_mail_send(startargs[1], cpu_logical_map(cpu), 1); in csr_ipi_write_buf()
115 csr_mail_send(startargs[0], cpu_logical_map(cpu), 0); in csr_ipi_write_buf()
118 static u32 legacy_ipi_read_clear(int cpu) in legacy_ipi_read_clear() argument
123 action = readl_relaxed(ipi_status0_regs[cpu_logical_map(cpu)]); in legacy_ipi_read_clear()
125 writel_relaxed(action, ipi_clear0_regs[cpu_logical_map(cpu)]); in legacy_ipi_read_clear()
131 static void legacy_ipi_write_action(int cpu, u32 action) in legacy_ipi_write_action() argument
133 writel_relaxed((u32)action, ipi_set0_regs[cpu]); in legacy_ipi_write_action()
137 static void legacy_ipi_write_enable(int cpu) in legacy_ipi_write_enable() argument
139 writel_relaxed(0xffffffff, ipi_en0_regs[cpu_logical_map(cpu)]); in legacy_ipi_write_enable()
142 static void legacy_ipi_clear_buf(int cpu) in legacy_ipi_clear_buf() argument
144 writeq_relaxed(0, ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0); in legacy_ipi_clear_buf()
147 static void legacy_ipi_write_buf(int cpu, struct task_struct *idle) in legacy_ipi_write_buf() argument
151 /* startargs[] are initial PC, SP and GP for secondary CPU */ in legacy_ipi_write_buf()
157 pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n", in legacy_ipi_write_buf()
158 cpu, startargs[0], startargs[1], startargs[2]); in legacy_ipi_write_buf()
161 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x18); in legacy_ipi_write_buf()
163 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x10); in legacy_ipi_write_buf()
165 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x8); in legacy_ipi_write_buf()
167 ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0); in legacy_ipi_write_buf()
371 static void loongson3_send_ipi_single(int cpu, unsigned int action) in loongson3_send_ipi_single() argument
373 ipi_write_action(cpu_logical_map(cpu), (u32)action); in loongson3_send_ipi_single()
388 int i, cpu = smp_processor_id(); in loongson3_ipi_interrupt() local
391 action = ipi_read_clear(cpu); in loongson3_ipi_interrupt()
403 BUG_ON(cpu != 0); in loongson3_ipi_interrupt()
422 unsigned int cpu = smp_processor_id(); in loongson3_init_secondary() local
428 ipi_write_enable(cpu); in loongson3_init_secondary()
430 per_cpu(cpu_state, cpu) = CPU_ONLINE; in loongson3_init_secondary()
431 cpu_set_core(&cpu_data[cpu], in loongson3_init_secondary()
432 cpu_logical_map(cpu) % loongson_sysconf.cores_per_package); in loongson3_init_secondary()
433 cpu_data[cpu].package = in loongson3_init_secondary()
434 cpu_logical_map(cpu) / loongson_sysconf.cores_per_package; in loongson3_init_secondary()
437 core0_c0count[cpu] = 0; in loongson3_init_secondary()
439 while (!core0_c0count[cpu]) { in loongson3_init_secondary()
446 if (cpu_data[cpu].package) in loongson3_init_secondary()
447 initcount = core0_c0count[cpu] + i; in loongson3_init_secondary()
449 initcount = core0_c0count[cpu] + i/2; in loongson3_init_secondary()
456 int cpu = smp_processor_id(); in loongson3_smp_finish() local
460 ipi_clear_buf(cpu); in loongson3_smp_finish()
462 pr_info("CPU#%d finished, CP0_ST=%x\n", in loongson3_smp_finish()
477 /* Reserved physical CPU cores */ in loongson3_smp_setup()
478 __cpu_number_map[i] = -1; in loongson3_smp_setup()
489 pr_info("Detected %i available CPU(s)\n", num); in loongson3_smp_setup()
492 __cpu_logical_map[num] = -1; in loongson3_smp_setup()
521 static int loongson3_boot_secondary(int cpu, struct task_struct *idle) in loongson3_boot_secondary() argument
523 pr_info("Booting CPU#%d...\n", cpu); in loongson3_boot_secondary()
525 ipi_write_buf(cpu, idle); in loongson3_boot_secondary()
535 unsigned int cpu = smp_processor_id(); in loongson3_cpu_disable() local
537 set_cpu_online(cpu, false); in loongson3_cpu_disable()
548 static void loongson3_cpu_die(unsigned int cpu) in loongson3_cpu_die() argument
550 while (per_cpu(cpu_state, cpu) != CPU_DEAD) in loongson3_cpu_die()
556 /* To shutdown a core in Loongson 3, the target core should go to CKSEG1 and
557 * flush all L1 entries at first. Then, another core (usually Core 0) can
558 * safely disable the clock of the target core. loongson3_play_dead() is
564 register long cpuid, core, node, count; in loongson3_type1_play_dead() local
579 " addiu %[sets], %[sets], -1 \n" in loongson3_type1_play_dead()
598 " andi %[core], %[cpuid], 0x3 \n" in loongson3_type1_play_dead()
599 " sll %[core], 8 \n" /* get core id */ in loongson3_type1_play_dead()
600 " or %[base], %[base], %[core] \n" in loongson3_type1_play_dead()
606 " addiu %[count], -1 \n" in loongson3_type1_play_dead()
616 : [core] "=&r" (core), [node] "=&r" (node), in loongson3_type1_play_dead()
626 register long cpuid, core, node, count; in loongson3_type2_play_dead() local
641 " addiu %[sets], %[sets], -1 \n" in loongson3_type2_play_dead()
660 " andi %[core], %[cpuid], 0x3 \n" in loongson3_type2_play_dead()
661 " sll %[core], 8 \n" /* get core id */ in loongson3_type2_play_dead()
662 " or %[base], %[base], %[core] \n" in loongson3_type2_play_dead()
670 " addiu %[count], -1 \n" in loongson3_type2_play_dead()
680 : [core] "=&r" (core), [node] "=&r" (node), in loongson3_type2_play_dead()
690 register long cpuid, core, node, count; in loongson3_type3_play_dead() local
705 " addiu %[sets], %[sets], -1 \n" in loongson3_type3_play_dead()
725 " addiu %[vsets], %[vsets], -1 \n" in loongson3_type3_play_dead()
745 " andi %[core], %[cpuid], 0x3 \n" in loongson3_type3_play_dead()
746 " sll %[core], 8 \n" /* get core id */ in loongson3_type3_play_dead()
747 " or %[base], %[base], %[core] \n" in loongson3_type3_play_dead()
753 " addiu %[count], -1 \n" in loongson3_type3_play_dead()
754 " lw %[initfunc], 0x20(%[base]) \n" /* check lower 32-bit as jump indicator */ in loongson3_type3_play_dead()
757 " ld %[initfunc], 0x20(%[base]) \n" /* get PC (whole 64-bit) via mailbox */ in loongson3_type3_play_dead()
764 : [core] "=&r" (core), [node] "=&r" (node), in loongson3_type3_play_dead()
774 unsigned int cpu = smp_processor_id(); in play_dead() local
810 state_addr = &per_cpu(cpu_state, cpu); in play_dead()
816 static int loongson3_disable_clock(unsigned int cpu) in loongson3_disable_clock() argument
818 uint64_t core_id = cpu_core(&cpu_data[cpu]); in loongson3_disable_clock()
819 uint64_t package_id = cpu_data[cpu].package; in loongson3_disable_clock()
830 static int loongson3_enable_clock(unsigned int cpu) in loongson3_enable_clock() argument
832 uint64_t core_id = cpu_core(&cpu_data[cpu]); in loongson3_enable_clock()
833 uint64_t package_id = cpu_data[cpu].package; in loongson3_enable_clock()