1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/cpu.h>
18 #include <asm/mips-cps.h>
21 #include <asm/pm-cps.h>
24 #include <asm/smp-cps.h>
32 static unsigned __init core_vpe_count(unsigned int cluster, unsigned core)  in core_vpe_count()  argument
34 	return min(smp_max_threads, mips_cps_numvps(cluster, core));  in core_vpe_count()
60 			/* Use the number of VPEs in cluster 0 core 0 for smp_num_siblings */  in cps_smp_setup()
64 			for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {  in cps_smp_setup()
77 	/* Indicate present CPUs (CPU being synonymous with VPE) */  in cps_smp_setup()
88 	/* Core 0 is powered up (we're running on it) */  in cps_smp_setup()
91 	/* Initialise core 0 */  in cps_smp_setup()
94 	/* Make core 0 coherent with everything */  in cps_smp_setup()
103 	/* If we have an FPU, enroll ourselves in the FPU-full mask */  in cps_smp_setup()
117 	/* Detect whether the CCA is unsuited to multi-core SMP */  in cps_prepare_cpus()
122 		/* The CCA is coherent, multi-core is fine */  in cps_prepare_cpus()
127 		/* CCA is not coherent, multi-core is not usable */  in cps_prepare_cpus()
131 	/* Warn the user if the CCA prevents multi-core */  in cps_prepare_cpus()
143 		pr_warn("Using only one core due to %s%s%s\n",  in cps_prepare_cpus()
160 		     (void *)entry_code - (void *)&mips_cps_core_entry);  in cps_prepare_cpus()
163 	/* Allocate core boot configuration structs */  in cps_prepare_cpus()
185 	/* Mark this CPU as booted */  in cps_prepare_cpus()
207 static void boot_core(unsigned int core, unsigned int vpe_id)  in boot_core()  argument
212 	/* Select the appropriate core */  in boot_core()
213 	mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);  in boot_core()
224 	/* Ensure the core can access the GCRs */  in boot_core()
225 	set_gcr_access(1 << core);  in boot_core()
228 		/* Reset the core */  in boot_core()
229 		mips_cpc_lock_other(core);  in boot_core()
238 			 * core leaves reset.  in boot_core()
251 			/* U6 == coherent execution, ie. the core is up */  in boot_core()
257 				timeout--;  in boot_core()
262 			pr_warn("Waiting for core %u to start... STAT_CONF=0x%x\n",  in boot_core()
263 				core, stat);  in boot_core()
269 		/* Take the core out of reset */  in boot_core()
275 	/* The core is now powered up */  in boot_core()
276 	bitmap_set(core_power, core, 1);  in boot_core()
281 	unsigned core = cpu_core(&current_cpu_data);  in remote_vpe_boot()  local
282 	struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];  in remote_vpe_boot()
287 static int cps_boot_secondary(int cpu, struct task_struct *idle)  in cps_boot_secondary()  argument
289 	unsigned core = cpu_core(&cpu_data[cpu]);  in cps_boot_secondary()  local
290 	unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);  in cps_boot_secondary()
291 	struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];  in cps_boot_secondary()
292 	struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];  in cps_boot_secondary()
298 	if (cpu_cluster(&cpu_data[cpu]) != cpu_cluster(&raw_current_cpu_data))  in cps_boot_secondary()
299 		return -ENOSYS;  in cps_boot_secondary()
301 	vpe_cfg->pc = (unsigned long)&smp_bootstrap;  in cps_boot_secondary()
302 	vpe_cfg->sp = __KSTK_TOS(idle);  in cps_boot_secondary()
303 	vpe_cfg->gp = (unsigned long)task_thread_info(idle);  in cps_boot_secondary()
305 	atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);  in cps_boot_secondary()
309 	if (!test_bit(core, core_power)) {  in cps_boot_secondary()
310 		/* Boot a VPE on a powered down core */  in cps_boot_secondary()
311 		boot_core(core, vpe_id);  in cps_boot_secondary()
316 		mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);  in cps_boot_secondary()
322 	if (!cpus_are_siblings(cpu, smp_processor_id())) {  in cps_boot_secondary()
323 		/* Boot a VPE on another powered up core */  in cps_boot_secondary()
325 			if (!cpus_are_siblings(cpu, remote))  in cps_boot_secondary()
331 			pr_crit("No online CPU in core %u to start CPU%d\n",  in cps_boot_secondary()
332 				core, cpu);  in cps_boot_secondary()
339 			panic("Failed to call remote CPU\n");  in cps_boot_secondary()
345 	/* Boot a VPE on this core */  in cps_boot_secondary()
354 	int core = cpu_core(&current_cpu_data);  in cps_init_secondary()  local
356 	/* Disable MT - we only want to run 1 TC per VPE */  in cps_init_secondary()
371 	if (core > 0 && !read_gcr_cl_coherence())  in cps_init_secondary()
372 		pr_warn("Core %u is not in coherent domain\n", core);  in cps_init_secondary()
387 	/* If we have an FPU, enroll ourselves in the FPU-full mask */  in cps_smp_finish()
404 	unsigned int cpu, core, vpe_id;  in cps_shutdown_this_cpu()  local
406 	cpu = smp_processor_id();  in cps_shutdown_this_cpu()
407 	core = cpu_core(&cpu_data[cpu]);  in cps_shutdown_this_cpu()
410 		vpe_id = cpu_vpe_id(&cpu_data[cpu]);  in cps_shutdown_this_cpu()
412 		pr_debug("Halting core %d VP%d\n", core, vpe_id);  in cps_shutdown_this_cpu()
425 			pr_debug("Gating power to core %d\n", core);  in cps_shutdown_this_cpu()
426 			/* Power down the core */  in cps_shutdown_this_cpu()
450 	unsigned cpu = smp_processor_id();  in cps_cpu_disable()  local
454 		return -EINVAL;  in cps_cpu_disable()
457 	atomic_sub(1 << cpu_vpe_id(&current_cpu_data), &core_cfg->vpe_mask);  in cps_cpu_disable()
459 	set_cpu_online(cpu, false);  in cps_cpu_disable()
471 	unsigned int cpu;  in play_dead()  local
475 	cpu = smp_processor_id();  in play_dead()
478 	pr_debug("CPU%d going offline\n", cpu);  in play_dead()
481 		/* Look for another online VPE within the core */  in play_dead()
483 			if (!cpus_are_siblings(cpu, cpu_death_sibling))  in play_dead()
487 			 * There is an online VPE within the core. Just halt  in play_dead()
488 			 * this TC and leave the core alone.  in play_dead()
500 	panic("Failed to offline CPU %u", cpu);  in play_dead()
505 	unsigned cpu = (unsigned long)ptr_cpu;  in wait_for_sibling_halt()  local
506 	unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);  in wait_for_sibling_halt()
518 static void cps_cpu_die(unsigned int cpu) { }  in cps_cpu_die()  argument
520 static void cps_cleanup_dead_cpu(unsigned cpu)  in cps_cleanup_dead_cpu()  argument
522 	unsigned core = cpu_core(&cpu_data[cpu]);  in cps_cleanup_dead_cpu()  local
523 	unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]);  in cps_cleanup_dead_cpu()
529 	 * Now wait for the CPU to actually offline. Without doing this that  in cps_cleanup_dead_cpu()
532 	 *   - Onlining the CPU again.  in cps_cleanup_dead_cpu()
533 	 *   - Powering down the core if another VPE within it is offlined.  in cps_cleanup_dead_cpu()
534 	 *   - A sibling VPE entering a non-coherent state.  in cps_cleanup_dead_cpu()
536 	 * In the non-MT halt case (ie. infinite loop) the CPU is doing nothing  in cps_cleanup_dead_cpu()
541 		 * Wait for the core to enter a powered down or clock gated  in cps_cleanup_dead_cpu()
543 		 * in which case the CPC will refuse to power down the core.  in cps_cleanup_dead_cpu()
547 			mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL);  in cps_cleanup_dead_cpu()
548 			mips_cpc_lock_other(core);  in cps_cleanup_dead_cpu()
561 			 * The core ought to have powered down, but didn't &  in cps_cleanup_dead_cpu()
568 			 * the hope that the core is doing nothing harmful &  in cps_cleanup_dead_cpu()
572 				 "CPU%u hasn't powered down, seq. state %u\n",  in cps_cleanup_dead_cpu()
573 				 cpu, stat))  in cps_cleanup_dead_cpu()
577 		/* Indicate the core is powered off */  in cps_cleanup_dead_cpu()
578 		bitmap_clear(core_power, core, 1);  in cps_cleanup_dead_cpu()
581 		 * Have a CPU with access to the offlined CPUs registers wait  in cps_cleanup_dead_cpu()
586 					       (void *)(unsigned long)cpu, 1);  in cps_cleanup_dead_cpu()
588 			panic("Failed to call remote sibling CPU\n");  in cps_cleanup_dead_cpu()
591 			mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL);  in cps_cleanup_dead_cpu()
628 		return -ENODEV;  in register_cps_smp_ops()
631 	/* check we have a GIC - we need one for IPIs */  in register_cps_smp_ops()
634 		return -ENODEV;  in register_cps_smp_ops()