Lines Matching +full:32 +full:bit
56 BUILD_BUG_ON(sz != 32); \
67 BUILD_BUG_ON(sz != 32); \
85 /* For read-only shared bit-per-interrupt registers */
101 addr += (intr / 32) * sizeof(uint32_t); \
102 val = __raw_readl(addr) >> intr % 32; \
108 /* For read-write shared bit-per-interrupt registers */
118 __raw_writeq(BIT(intr % 64), addr); \
120 addr += (intr / 32) * sizeof(uint32_t); \
121 __raw_writel(BIT(intr % 32), addr); \
141 addr += (intr / 32) * sizeof(uint32_t); \
143 _val &= ~BIT(intr % 32); \
144 _val |= val << (intr % 32); \
149 /* For read-only local bit-per-interrupt registers */
156 /* For read-write local bit-per-interrupt registers */
164 GIC_ACCESSOR_RW(32, 0x000, config)
165 #define GIC_CONFIG_COUNTSTOP BIT(28)
172 GIC_ACCESSOR_RW(32, 0x010, counter_32l)
173 GIC_ACCESSOR_RW(32, 0x014, counter_32h)
193 GIC_ACCESSOR_RW(32, 0x280, wedge)
194 #define GIC_WEDGE_RW BIT(31)
210 GIC_ACCESSOR_RW_INTR_REG(32, 0x500, 0x4, map_pin)
211 #define GIC_MAP_PIN_MAP_TO_PIN BIT(31)
212 #define GIC_MAP_PIN_MAP_TO_NMI BIT(30)
216 GIC_ACCESSOR_RW_INTR_REG(32, 0x2000, 0x20, map_vp)
219 GIC_VX_ACCESSOR_RW(32, 0x000, ctl)
220 #define GIC_VX_CTL_FDC_ROUTABLE BIT(4)
221 #define GIC_VX_CTL_SWINT_ROUTABLE BIT(3)
222 #define GIC_VX_CTL_PERFCNT_ROUTABLE BIT(2)
223 #define GIC_VX_CTL_TIMER_ROUTABLE BIT(1)
224 #define GIC_VX_CTL_EIC BIT(0)
227 GIC_VX_ACCESSOR_RO(32, 0x004, pend)
230 GIC_VX_ACCESSOR_RO(32, 0x008, mask)
233 GIC_VX_ACCESSOR_RW(32, 0x00c, rmask)
236 GIC_VX_ACCESSOR_RW(32, 0x010, smask)
239 GIC_VX_ACCESSOR_RW_INTR_REG(32, 0x040, 0x4, map)
242 GIC_VX_ACCESSOR_RW(32, 0x040, wd_map)
245 GIC_VX_ACCESSOR_RW(32, 0x044, compare_map)
248 GIC_VX_ACCESSOR_RW(32, 0x048, timer_map)
251 GIC_VX_ACCESSOR_RW(32, 0x04c, fdc_map)
254 GIC_VX_ACCESSOR_RW(32, 0x050, perfctr_map)
257 GIC_VX_ACCESSOR_RW(32, 0x054, swint0_map)
260 GIC_VX_ACCESSOR_RW(32, 0x058, swint1_map)
263 GIC_VX_ACCESSOR_RW(32, 0x080, other)
267 GIC_VX_ACCESSOR_RO(32, 0x088, ident)
274 GIC_VX_ACCESSOR_RW_INTR_REG(32, 0x100, 0x4, eic_shadow_set)