Lines Matching +full:loongson +full:- +full:3
1 # SPDX-License-Identifier: GPL-2.0
135 bool "Generic board-agnostic MIPS kernel"
276 Build a generic DT-based kernel image that boots on select
277 BCM33xx cable modem chips, BCM63xx DSL chips, and BCM7xxx set-top
369 see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
370 DECstation porting pages on <http://decstation.unix-ag.org/>.
410 Olivetti M700-10 workstations.
446 bool "Loongson 32-bit family of machines"
449 This enables support for the Loongson-1 family of machines.
451 Loongson-1 is a family of 32-bit MIPS-compatible SoCs developed by
456 bool "Loongson-2E/F family of machines"
459 This enables the support of early Loongson-2E/F family of machines.
462 bool "Loongson 64-bit family of machines"
497 This enables the support of Loongson-2/3 family of machines.
499 Loongson-2 and Loongson-3 are 64-bit general-purpose processors with
500 GS264/GS464/GS464E/GS464V microarchitecture (except old Loongson-2E
501 and Loongson-2F which will be removed), developed by the Institute
566 Microchip PIC32 is a family of general-purpose 32 bit MIPS core
776 bool "Sibyte BCM91125C-CRhone"
786 bool "Sibyte BCM91125E-Rhone"
795 bool "Sibyte BCM91250A-SWARM"
808 bool "Sibyte BCM91250C2-LittleSur"
820 bool "Sibyte BCM91250E-Sentosa"
830 bool "Sibyte BCM91480B-BigSur"
879 The SNI RM200/300/400 are MIPS-based machines manufactured by
963 source "arch/mips/sgi-ip27/Kconfig"
966 source "arch/mips/cavium-octeon/Kconfig"
1244 bool "Loongson 64-bit CPU"
1266 The Loongson GSx64(GS264/GS464/GS464E/GS464V) series of processor
1268 including most 64-bit Loongson-2 (2H, 2K) and Loongson-3 (3A1000,
1269 3B1000, 3B1500, 3A2000, 3A3000 and 3A4000) processors. However, old
1270 Loongson-2E/2F is not covered here and will be removed in future.
1273 bool "New Loongson-3 CPU Enhancements"
1277 New Loongson-3 cores (since Loongson-3A R2, as opposed to Loongson-3A
1278 R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as
1279 FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPr2 ASE, User
1280 Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer),
1284 time. If you want a generic kernel to run on all Loongson 3 machines,
1285 please say 'N' here. If you want a high-performance kernel to run on
1286 new Loongson-3 machines only, please say 'Y' here.
1289 bool "Loongson-3 LLSC Workarounds"
1293 Loongson-3 processors have the llsc issues which require workarounds.
1299 bool "Emulate the CPUCFG instruction on older Loongson cores"
1303 Loongson-3A R4 and newer have the CPUCFG instruction available for
1305 option provides emulation of the instruction on older Loongson
1306 cores, back to Loongson-3A1000.
1311 bool "Loongson 2E"
1315 The Loongson 2E processor implements the MIPS III instruction set
1322 bool "Loongson 2F"
1326 The Loongson 2F processor implements the MIPS III instruction set
1329 Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller
1334 bool "Loongson 1B"
1339 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
1344 bool "Loongson 1C"
1349 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
1361 MIPS32 architecture. Most modern embedded systems with a 32-bit
1380 MIPS32 architecture. Most modern embedded systems with a 32-bit
1426 MIPS64 architecture. Many modern embedded systems with a 64-bit
1447 MIPS64 architecture. Many modern embedded systems with a 64-bit
1502 MMU with two-levels TLB, UCA, MSA, MDU core level features and system
1504 cache, IOCU/IOMMU (though might be unused depending on the system-
1529 MIPS Technologies R4300-series processors.
1538 MIPS Technologies R4000-series processors other than 4300, including
1556 MIPS Technologies R5000-series processors other than the Nevada.
1565 NEC VR5500 and VR5500A series processors implement 64-bit MIPS IV
1575 QED / PMC-Sierra RM52xx-series ("Nevada") processors.
1586 MIPS Technologies R10000-series processors.
1666 of lowmem (up to 3GB). If unsure, say 'N' here.
1692 64-bit addressing which in turn makes the PTEs 64-bit in size.
1703 bool "Loongson 2F Workarounds"
1708 Loongson 2F01 / 2F02 processors have the NOP & JUMP issues which
1711 -mfix-loongson2f-nop and -mfix-loongson2f-jump options.
1713 Loongson 2F03 and later have fixed these issues and no workarounds
1882 # CPU may reorder R->R, R->W, W->R, W->W
1890 # CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
1990 actually benefits from 64-bit processing or if your machine has
1992 menu if your system does not support both 32-bit and 64-bit kernels.
1995 bool "32-bit kernel"
1999 Select this option if you want to build a 32-bit kernel.
2002 bool "64-bit kernel"
2005 Select this option if you want to build a 64-bit kernel.
2030 This is only used if non-zero.
2041 R3000-family processors this is the only available page size. Using
2061 all non-R3000 family processors. Note that you will need a suitable
2080 all non-R3000 family processor. Not that at the time of this
2110 # Support for a MIPS32 / MIPS64 style S-caches
2189 <http://www.imgtec.com/mips/mips-multithreading.asp>.
2210 bool "Dynamic FPU affinity for FP-intensive threads"
2215 bool "MIPS R2-to-R6 emulator"
2220 Choose this option if you want to run non-R6 MIPS userland code.
2223 The only reason this is a build-time option is to save ~14K from the
2395 # CPU non-features
2400 # - The `daddi' instruction fails to trap on overflow.
2404 # - The `daddiu' instruction can produce an incorrect result.
2416 # - A double-word or a variable shift may give an incorrect result
2423 # - A double-word or a variable shift may give an incorrect result
2428 # - An integer division may give an incorrect result if started in
2438 # - A double-word or a variable shift may give an incorrect result
2468 # interrupts during indexed I-cache flushes seems to be sufficient to deal
2520 # The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
2522 # I-cache line worth of instructions being fetched may case spurious
2528 # may cause ll / sc and lld / scd sequences to execute non-atomically.
2537 # - Highmem only makes sense for the 32-bit kernel.
2538 # - The current highmem code will only work properly on physically indexed
2545 # - We use SYS_SUPPORTS_HIGHMEM to offer highmem only for systems where we
2569 This option must be set if a kernel might be executed on a MIPS16-
2571 words, it makes the kernel MIPS16-tolerant.
2590 Say Y to compile the kernel to support NUMA (Non-Uniform Memory
2660 This is limited by the size of KSEG0, 256Mb on 32-bit or 1Gb with
2661 EVA or 64-bit. The default is 16Mb.
2688 bool "Multi-Processing support"
2695 If you say N here, the kernel will run on uni- and multiprocessor
2704 See also the SMP-HOWTO available at
2710 bool "Support for hot-pluggable CPUs"
2744 int "Maximum number of CPUs (2-256)"
2754 kernel will support. The maximum supported value is 32 for 32-bit
2755 kernel and 64 for 64-bit kernels; the minimum value which makes
2759 This is purely to save memory - each supported CPU adds
2876 passed to the panic-ed kernel).
2879 bool "Support for O32 binaries using 64-bit FP" if !CPU_MIPSR6
2882 When this is enabled, the kernel will support use of 64-bit floating
2884 EF_MIPS_FP64 ELF header flag (typically built with -mfp64). On
2885 32-bit MIPS systems this support is at the cost of increasing the
2888 will require 64-bit floating point, you may wish to reduce the size
2930 objcopy --update-section .appended_dtb=<filename>.dtb vmlinux
2990 default 3 if 64BIT && (!PAGE_SIZE_64KB || MIPS_VA_BITS_48)
3024 <http://www.computer-refuge.org/classiccmp/ftp.digital.com/pub/DEC/TriAdd/>
3026 <http://www.linux-mips.org/wiki/DECstation>
3070 32-bit binaries as used by the 32-bit Linux/MIPS port. Most of
3083 64-bit binaries using 32-bit quantities for addressing and certain
3084 data that would normally be 64-bit. They are used in special
3091 depends on $(cc-option,-mno-branch-likely)
3093 # https://github.com/llvm/llvm-project/issues/61045