Lines Matching +full:i +full:- +full:tlb +full:- +full:size

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
4  * Copyright (C) 2008-2009 PetaLogix
27 	unsigned long    w:1;	/* Write-thru cache mode */
28 	unsigned long    i:1;	/* Cache inhibited */  member
43 	unsigned long    t:1;	/* Normal or I/O  type */
46 	unsigned long    n:1;	/* No-execute */
51 extern void _tlbie(unsigned long va);	/* invalidate a TLB entry */
52 extern void _tlbia(void);		/* invalidate all TLB entries */
55  * tlb_skip size stores actual number skipped TLBs from TLB0 - every directy TLB
56  * mapping has to increase tlb_skip size.
62  * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The
63  * instruction and data sides share a unified, 64-entry, semi-associative
64  * TLB which is maintained totally under software control. In addition, the
65  * instruction side has a hardware-managed, 2,4, or 8-entry, fully-associative
66  * TLB which serves as a first level to the shared TLB. These two TLBs are
72 /* For cases when you want to skip some TLB entries */
75 /* Use the last TLB for temporary access to LMB */
79  * TLB entries are defined by a "high" tag portion and a "low" data
80  * portion. The data portion is 32-bits.
82  * TLB entries are managed entirely under software control by reading,
113 #  define TLB_W			0x00000008 /* Caching is write-through */