Lines Matching +full:0 +full:x392
23 #define REG_ZERO 0x0
24 #define REG_RA 0x1
25 #define REG_TP 0x2
26 #define REG_SP 0x3
27 #define REG_A0 0x4 /* Reused as V0 for return value */
28 #define REG_A1 0x5 /* Reused as V1 for return value */
29 #define REG_A2 0x6
30 #define REG_A3 0x7
31 #define REG_A4 0x8
32 #define REG_A5 0x9
33 #define REG_A6 0xa
34 #define REG_A7 0xb
35 #define REG_T0 0xc
36 #define REG_T1 0xd
37 #define REG_T2 0xe
38 #define REG_T3 0xf
39 #define REG_T4 0x10
40 #define REG_T5 0x11
41 #define REG_T6 0x12
42 #define REG_T7 0x13
43 #define REG_T8 0x14
44 #define REG_U0 0x15 /* Kernel uses it as percpu base */
45 #define REG_FP 0x16
46 #define REG_S0 0x17
47 #define REG_S1 0x18
48 #define REG_S2 0x19
49 #define REG_S3 0x1a
50 #define REG_S4 0x1b
51 #define REG_S5 0x1c
52 #define REG_S6 0x1d
53 #define REG_S7 0x1e
54 #define REG_S8 0x1f
59 #define LOONGARCH_CPUCFG0 0x0
60 #define CPUCFG0_PRID GENMASK(31, 0)
62 #define LOONGARCH_CPUCFG1 0x1
63 #define CPUCFG1_ISGR32 BIT(0)
77 #define LOONGARCH_CPUCFG2 0x2
78 #define CPUCFG2_FP BIT(0)
97 #define LOONGARCH_CPUCFG3 0x3
98 #define CPUCFG3_CCDMA BIT(0)
111 #define LOONGARCH_CPUCFG4 0x4
112 #define CPUCFG4_CCFREQ GENMASK(31, 0)
114 #define LOONGARCH_CPUCFG5 0x5
115 #define CPUCFG5_CCMUL GENMASK(15, 0)
118 #define LOONGARCH_CPUCFG6 0x6
119 #define CPUCFG6_PMP BIT(0)
125 #define LOONGARCH_CPUCFG16 0x10
126 #define CPUCFG16_L1_IUPRE BIT(0)
144 #define LOONGARCH_CPUCFG17 0x11
145 #define LOONGARCH_CPUCFG18 0x12
146 #define LOONGARCH_CPUCFG19 0x13
147 #define LOONGARCH_CPUCFG20 0x14
148 #define CPUCFG_CACHE_WAYS_M GENMASK(15, 0)
151 #define CPUCFG_CACHE_WAYS 0
155 #define LOONGARCH_CPUCFG48 0x30
156 #define CPUCFG48_MCSR_LCK BIT(0)
182 #define LOONGARCH_CSR_CRMD 0x0 /* Current mode info */
184 #define CSR_CRMD_WE (_ULCAST_(0x1) << CSR_CRMD_WE_SHIFT)
187 #define CSR_CRMD_DACM (_ULCAST_(0x3) << CSR_CRMD_DACM_SHIFT)
190 #define CSR_CRMD_DACF (_ULCAST_(0x3) << CSR_CRMD_DACF_SHIFT)
192 #define CSR_CRMD_PG (_ULCAST_(0x1) << CSR_CRMD_PG_SHIFT)
194 #define CSR_CRMD_DA (_ULCAST_(0x1) << CSR_CRMD_DA_SHIFT)
196 #define CSR_CRMD_IE (_ULCAST_(0x1) << CSR_CRMD_IE_SHIFT)
197 #define CSR_CRMD_PLV_SHIFT 0
199 #define CSR_CRMD_PLV (_ULCAST_(0x3) << CSR_CRMD_PLV_SHIFT)
201 #define PLV_KERN 0
203 #define PLV_MASK 0x3
205 #define LOONGARCH_CSR_PRMD 0x1 /* Prev-exception mode info */
207 #define CSR_PRMD_PWE (_ULCAST_(0x1) << CSR_PRMD_PWE_SHIFT)
209 #define CSR_PRMD_PIE (_ULCAST_(0x1) << CSR_PRMD_PIE_SHIFT)
210 #define CSR_PRMD_PPLV_SHIFT 0
212 #define CSR_PRMD_PPLV (_ULCAST_(0x3) << CSR_PRMD_PPLV_SHIFT)
214 #define LOONGARCH_CSR_EUEN 0x2 /* Extended unit enable */
216 #define CSR_EUEN_LBTEN (_ULCAST_(0x1) << CSR_EUEN_LBTEN_SHIFT)
218 #define CSR_EUEN_LASXEN (_ULCAST_(0x1) << CSR_EUEN_LASXEN_SHIFT)
220 #define CSR_EUEN_LSXEN (_ULCAST_(0x1) << CSR_EUEN_LSXEN_SHIFT)
221 #define CSR_EUEN_FPEN_SHIFT 0
222 #define CSR_EUEN_FPEN (_ULCAST_(0x1) << CSR_EUEN_FPEN_SHIFT)
224 #define LOONGARCH_CSR_MISC 0x3 /* Misc config */
226 #define LOONGARCH_CSR_ECFG 0x4 /* Exception config */
230 #define CSR_ECFG_VS (_ULCAST_(0x7) << CSR_ECFG_VS_SHIFT)
231 #define CSR_ECFG_IM_SHIFT 0
233 #define CSR_ECFG_IM (_ULCAST_(0x3fff) << CSR_ECFG_IM_SHIFT)
235 #define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */
238 #define CSR_ESTAT_ESUBCODE (_ULCAST_(0x1ff) << CSR_ESTAT_ESUBCODE_SHIFT)
241 #define CSR_ESTAT_EXC (_ULCAST_(0x3f) << CSR_ESTAT_EXC_SHIFT)
242 #define CSR_ESTAT_IS_SHIFT 0
244 #define CSR_ESTAT_IS (_ULCAST_(0x3fff) << CSR_ESTAT_IS_SHIFT)
246 #define LOONGARCH_CSR_ERA 0x6 /* ERA */
248 #define LOONGARCH_CSR_BADV 0x7 /* Bad virtual address */
250 #define LOONGARCH_CSR_BADI 0x8 /* Bad instruction */
252 #define LOONGARCH_CSR_EENTRY 0xc /* Exception entry */
255 #define LOONGARCH_CSR_TLBIDX 0x10 /* TLB Index, EHINV, PageSize, NP */
260 #define CSR_TLBIDX_PS (_ULCAST_(0x3f) << CSR_TLBIDX_PS_SHIFT)
261 #define CSR_TLBIDX_IDX_SHIFT 0
263 #define CSR_TLBIDX_IDX (_ULCAST_(0xfff) << CSR_TLBIDX_IDX_SHIFT)
264 #define CSR_TLBIDX_SIZEM 0x3f000000
266 #define CSR_TLBIDX_IDXM 0xfff
269 #define LOONGARCH_CSR_TLBEHI 0x11 /* TLB EntryHi */
271 #define LOONGARCH_CSR_TLBELO0 0x12 /* TLB EntryLo0 */
273 #define CSR_TLBLO0_RPLV (_ULCAST_(0x1) << CSR_TLBLO0_RPLV_SHIFT)
275 #define CSR_TLBLO0_NX (_ULCAST_(0x1) << CSR_TLBLO0_NX_SHIFT)
277 #define CSR_TLBLO0_NR (_ULCAST_(0x1) << CSR_TLBLO0_NR_SHIFT)
280 #define CSR_TLBLO0_PFN (_ULCAST_(0xfffffffff) << CSR_TLBLO0_PFN_SHIFT)
282 #define CSR_TLBLO0_GLOBAL (_ULCAST_(0x1) << CSR_TLBLO0_GLOBAL_SHIFT)
285 #define CSR_TLBLO0_CCA (_ULCAST_(0x3) << CSR_TLBLO0_CCA_SHIFT)
288 #define CSR_TLBLO0_PLV (_ULCAST_(0x3) << CSR_TLBLO0_PLV_SHIFT)
290 #define CSR_TLBLO0_WE (_ULCAST_(0x1) << CSR_TLBLO0_WE_SHIFT)
291 #define CSR_TLBLO0_V_SHIFT 0
292 #define CSR_TLBLO0_V (_ULCAST_(0x1) << CSR_TLBLO0_V_SHIFT)
294 #define LOONGARCH_CSR_TLBELO1 0x13 /* TLB EntryLo1 */
296 #define CSR_TLBLO1_RPLV (_ULCAST_(0x1) << CSR_TLBLO1_RPLV_SHIFT)
298 #define CSR_TLBLO1_NX (_ULCAST_(0x1) << CSR_TLBLO1_NX_SHIFT)
300 #define CSR_TLBLO1_NR (_ULCAST_(0x1) << CSR_TLBLO1_NR_SHIFT)
303 #define CSR_TLBLO1_PFN (_ULCAST_(0xfffffffff) << CSR_TLBLO1_PFN_SHIFT)
305 #define CSR_TLBLO1_GLOBAL (_ULCAST_(0x1) << CSR_TLBLO1_GLOBAL_SHIFT)
308 #define CSR_TLBLO1_CCA (_ULCAST_(0x3) << CSR_TLBLO1_CCA_SHIFT)
311 #define CSR_TLBLO1_PLV (_ULCAST_(0x3) << CSR_TLBLO1_PLV_SHIFT)
313 #define CSR_TLBLO1_WE (_ULCAST_(0x1) << CSR_TLBLO1_WE_SHIFT)
314 #define CSR_TLBLO1_V_SHIFT 0
315 #define CSR_TLBLO1_V (_ULCAST_(0x1) << CSR_TLBLO1_V_SHIFT)
317 #define LOONGARCH_CSR_GTLBC 0x15 /* Guest TLB control */
321 #define CSR_GTLBC_TGID (_ULCAST_(0xff) << CSR_GTLBC_TGID_SHIFT)
323 #define CSR_GTLBC_TOTI (_ULCAST_(0x1) << CSR_GTLBC_TOTI_SHIFT)
325 #define CSR_GTLBC_USETGID (_ULCAST_(0x1) << CSR_GTLBC_USETGID_SHIFT)
326 #define CSR_GTLBC_GMTLBSZ_SHIFT 0
328 #define CSR_GTLBC_GMTLBSZ (_ULCAST_(0x3f) << CSR_GTLBC_GMTLBSZ_SHIFT)
330 #define LOONGARCH_CSR_TRGP 0x16 /* TLBR read guest info */
333 #define CSR_TRGP_RID (_ULCAST_(0xff) << CSR_TRGP_RID_SHIFT)
334 #define CSR_TRGP_GTLB_SHIFT 0
337 #define LOONGARCH_CSR_ASID 0x18 /* ASID */
340 #define CSR_ASID_BIT (_ULCAST_(0xff) << CSR_ASID_BIT_SHIFT)
341 #define CSR_ASID_ASID_SHIFT 0
343 #define CSR_ASID_ASID (_ULCAST_(0x3ff) << CSR_ASID_ASID_SHIFT)
345 #define LOONGARCH_CSR_PGDL 0x19 /* Page table base address when VA[VALEN-1] = 0 */
347 #define LOONGARCH_CSR_PGDH 0x1a /* Page table base address when VA[VALEN-1] = 1 */
349 #define LOONGARCH_CSR_PGD 0x1b /* Page table base */
351 #define LOONGARCH_CSR_PWCTL0 0x1c /* PWCtl0 */
354 #define CSR_PWCTL0_PTEW (_ULCAST_(0x3) << CSR_PWCTL0_PTEW_SHIFT)
357 #define CSR_PWCTL0_DIR1WIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_DIR1WIDTH_SHIFT)
360 #define CSR_PWCTL0_DIR1BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR1BASE_SHIFT)
363 #define CSR_PWCTL0_DIR0WIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_DIR0WIDTH_SHIFT)
366 #define CSR_PWCTL0_DIR0BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR0BASE_SHIFT)
369 #define CSR_PWCTL0_PTWIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_PTWIDTH_SHIFT)
370 #define CSR_PWCTL0_PTBASE_SHIFT 0
372 #define CSR_PWCTL0_PTBASE (_ULCAST_(0x1f) << CSR_PWCTL0_PTBASE_SHIFT)
374 #define LOONGARCH_CSR_PWCTL1 0x1d /* PWCtl1 */
377 #define CSR_PWCTL1_PTW (_ULCAST_(0x1) << CSR_PWCTL1_PTW_SHIFT)
380 #define CSR_PWCTL1_DIR3WIDTH (_ULCAST_(0x1f) << CSR_PWCTL1_DIR3WIDTH_SHIFT)
383 #define CSR_PWCTL1_DIR3BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR3BASE_SHIFT)
386 #define CSR_PWCTL1_DIR2WIDTH (_ULCAST_(0x1f) << CSR_PWCTL1_DIR2WIDTH_SHIFT)
387 #define CSR_PWCTL1_DIR2BASE_SHIFT 0
389 #define CSR_PWCTL1_DIR2BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR2BASE_SHIFT)
391 #define LOONGARCH_CSR_STLBPGSIZE 0x1e
393 #define CSR_STLBPGSIZE_PS (_ULCAST_(0x3f))
395 #define LOONGARCH_CSR_RVACFG 0x1f
397 #define CSR_RVACFG_RDVA (_ULCAST_(0xf))
400 #define LOONGARCH_CSR_CPUID 0x20 /* CPU core id */
402 #define CSR_CPUID_COREID _ULCAST_(0x1ff)
404 #define LOONGARCH_CSR_PRCFG1 0x21 /* Config1 */
410 #define CSR_CONF1_TMRBITS (_ULCAST_(0xff) << CSR_CONF1_TMRBITS_SHIFT)
412 #define CSR_CONF1_KSNUM _ULCAST_(0xf)
414 #define LOONGARCH_CSR_PRCFG2 0x22 /* Config2 */
415 #define CSR_CONF2_PGMASK_SUPP 0x3ffff000
417 #define LOONGARCH_CSR_PRCFG3 0x23 /* Config3 */
420 #define CSR_CONF3_STLBIDX (_ULCAST_(0x3f) << CSR_CONF3_STLBIDX_SHIFT)
423 #define CSR_CONF3_STLBWAYS (_ULCAST_(0xff) << CSR_CONF3_STLBWAYS_SHIFT)
426 #define CSR_CONF3_MTLBSIZE (_ULCAST_(0xff) << CSR_CONF3_MTLBSIZE_SHIFT)
427 #define CSR_CONF3_TLBTYPE_SHIFT 0
429 #define CSR_CONF3_TLBTYPE (_ULCAST_(0xf) << CSR_CONF3_TLBTYPE_SHIFT)
432 #define LOONGARCH_CSR_KS0 0x30
433 #define LOONGARCH_CSR_KS1 0x31
434 #define LOONGARCH_CSR_KS2 0x32
435 #define LOONGARCH_CSR_KS3 0x33
436 #define LOONGARCH_CSR_KS4 0x34
437 #define LOONGARCH_CSR_KS5 0x35
438 #define LOONGARCH_CSR_KS6 0x36
439 #define LOONGARCH_CSR_KS7 0x37
440 #define LOONGARCH_CSR_KS8 0x38
446 #define EXC_KSAVE_MASK (1 << 0 | 1 << 1 | 1 << 2)
458 #define LOONGARCH_CSR_TMID 0x40 /* Timer ID */
460 #define LOONGARCH_CSR_TCFG 0x41 /* Timer config */
463 #define CSR_TCFG_VAL (_ULCAST_(0x3fffffffffff) << CSR_TCFG_VAL_SHIFT)
465 #define CSR_TCFG_PERIOD (_ULCAST_(0x1) << CSR_TCFG_PERIOD_SHIFT)
466 #define CSR_TCFG_EN (_ULCAST_(0x1))
468 #define LOONGARCH_CSR_TVAL 0x42 /* Timer value */
470 #define LOONGARCH_CSR_CNTC 0x43 /* Timer offset */
472 #define LOONGARCH_CSR_TINTCLR 0x44 /* Timer interrupt clear */
473 #define CSR_TINTCLR_TI_SHIFT 0
477 #define LOONGARCH_CSR_GSTAT 0x50 /* Guest status */
481 #define CSR_GSTAT_GID (_ULCAST_(0xff) << CSR_GSTAT_GID_SHIFT)
484 #define CSR_GSTAT_GIDBIT (_ULCAST_(0x3f) << CSR_GSTAT_GIDBIT_SHIFT)
486 #define CSR_GSTAT_PVM (_ULCAST_(0x1) << CSR_GSTAT_PVM_SHIFT)
487 #define CSR_GSTAT_VM_SHIFT 0
488 #define CSR_GSTAT_VM (_ULCAST_(0x1) << CSR_GSTAT_VM_SHIFT)
490 #define LOONGARCH_CSR_GCFG 0x51 /* Guest config */
493 #define CSR_GCFG_GPERF (_ULCAST_(0x7) << CSR_GCFG_GPERF_SHIFT)
496 #define CSR_GCFG_GCI (_ULCAST_(0x3) << CSR_GCFG_GCI_SHIFT)
497 #define CSR_GCFG_GCI_ALL (_ULCAST_(0x0) << CSR_GCFG_GCI_SHIFT)
498 #define CSR_GCFG_GCI_HIT (_ULCAST_(0x1) << CSR_GCFG_GCI_SHIFT)
499 #define CSR_GCFG_GCI_SECURE (_ULCAST_(0x2) << CSR_GCFG_GCI_SHIFT)
501 #define CSR_GCFG_GCIP (_ULCAST_(0xf) << CSR_GCFG_GCIP_SHIFT)
502 #define CSR_GCFG_GCIP_ALL (_ULCAST_(0x1) << CSR_GCFG_GCIP_SHIFT)
503 #define CSR_GCFG_GCIP_HIT (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 1))
504 #define CSR_GCFG_GCIP_SECURE (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 2))
506 #define CSR_GCFG_TORU (_ULCAST_(0x1) << CSR_GCFG_TORU_SHIFT)
508 #define CSR_GCFG_TORUP (_ULCAST_(0x1) << CSR_GCFG_TORUP_SHIFT)
510 #define CSR_GCFG_TOP (_ULCAST_(0x1) << CSR_GCFG_TOP_SHIFT)
512 #define CSR_GCFG_TOPP (_ULCAST_(0x1) << CSR_GCFG_TOPP_SHIFT)
514 #define CSR_GCFG_TOE (_ULCAST_(0x1) << CSR_GCFG_TOE_SHIFT)
516 #define CSR_GCFG_TOEP (_ULCAST_(0x1) << CSR_GCFG_TOEP_SHIFT)
518 #define CSR_GCFG_TIT (_ULCAST_(0x1) << CSR_GCFG_TIT_SHIFT)
520 #define CSR_GCFG_TITP (_ULCAST_(0x1) << CSR_GCFG_TITP_SHIFT)
522 #define CSR_GCFG_SIT (_ULCAST_(0x1) << CSR_GCFG_SIT_SHIFT)
524 #define CSR_GCFG_SITP (_ULCAST_(0x1) << CSR_GCFG_SITP_SHIFT)
527 #define CSR_GCFG_MATC_MASK (_ULCAST_(0x3) << CSR_GCFG_MATC_SHITF)
528 #define CSR_GCFG_MATC_GUEST (_ULCAST_(0x0) << CSR_GCFG_MATC_SHITF)
529 #define CSR_GCFG_MATC_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATC_SHITF)
530 #define CSR_GCFG_MATC_NEST (_ULCAST_(0x2) << CSR_GCFG_MATC_SHITF)
532 #define CSR_GCFG_MATP_NEST (_ULCAST_(0x1) << CSR_GCFG_MATP_NEST_SHIFT)
534 #define CSR_GCFG_MATP_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATP_ROOT_SHIFT)
535 #define CSR_GCFG_MATP_GUEST_SHIFT 0
536 #define CSR_GCFG_MATP_GUEST (_ULCAST_(0x1) << CSR_GCFG_MATP_GUEST_SHIFT)
538 #define LOONGARCH_CSR_GINTC 0x52 /* Guest interrupt control */
541 #define CSR_GINTC_HC (_ULCAST_(0xff) << CSR_GINTC_HC_SHIFT)
544 #define CSR_GINTC_PIP (_ULCAST_(0xff) << CSR_GINTC_PIP_SHIFT)
545 #define CSR_GINTC_VIP_SHIFT 0
547 #define CSR_GINTC_VIP (_ULCAST_(0xff))
549 #define LOONGARCH_CSR_GCNTC 0x53 /* Guest timer offset */
552 #define LOONGARCH_CSR_LLBCTL 0x60 /* LLBit control */
553 #define CSR_LLBCTL_ROLLB_SHIFT 0
561 #define LOONGARCH_CSR_IMPCTL1 0x80 /* Loongson config1 */
564 #define CSR_MISPEC (_ULCAST_(0xff) << CSR_MISPEC_SHIFT)
600 #define CSR_DATAPRE_SHIFT 0
603 #define LOONGARCH_CSR_IMPCTL2 0x81 /* Loongson config2 */
604 #define CSR_FLUSH_MTLB_SHIFT 0
615 #define LOONGARCH_CSR_GNMI 0x82
618 #define LOONGARCH_CSR_TLBRENTRY 0x88 /* TLB refill exception entry */
619 #define LOONGARCH_CSR_TLBRBADV 0x89 /* TLB refill badvaddr */
620 #define LOONGARCH_CSR_TLBRERA 0x8a /* TLB refill ERA */
621 #define LOONGARCH_CSR_TLBRSAVE 0x8b /* KSave for TLB refill exception */
622 #define LOONGARCH_CSR_TLBRELO0 0x8c /* TLB refill entrylo0 */
623 #define LOONGARCH_CSR_TLBRELO1 0x8d /* TLB refill entrylo1 */
624 #define LOONGARCH_CSR_TLBREHI 0x8e /* TLB refill entryhi */
625 #define CSR_TLBREHI_PS_SHIFT 0
626 #define CSR_TLBREHI_PS (_ULCAST_(0x3f) << CSR_TLBREHI_PS_SHIFT)
627 #define LOONGARCH_CSR_TLBRPRMD 0x8f /* TLB refill mode info */
630 #define LOONGARCH_CSR_MERRCTL 0x90 /* MERRCTL */
631 #define LOONGARCH_CSR_MERRINFO1 0x91 /* MError info1 */
632 #define LOONGARCH_CSR_MERRINFO2 0x92 /* MError info2 */
633 #define LOONGARCH_CSR_MERRENTRY 0x93 /* MError exception entry */
634 #define LOONGARCH_CSR_MERRERA 0x94 /* MError exception ERA */
635 #define LOONGARCH_CSR_MERRSAVE 0x95 /* KSave for machine error exception */
637 #define LOONGARCH_CSR_CTAG 0x98 /* TagLo + TagHi */
639 #define LOONGARCH_CSR_PRID 0xc0
641 /* Shadow MCSR : 0xc0 ~ 0xff */
642 #define LOONGARCH_CSR_MCSR0 0xc0 /* CPUCFG0 and CPUCFG1 */
644 #define MCSR0_INT_IMPL 0
659 #define MCSR0_VABIT (_ULCAST_(0xff) << MCSR0_VABIT_SHIFT)
660 #define VABIT_DEFAULT 0x2f
663 #define MCSR0_PABIT (_ULCAST_(0xff) << MCSR0_PABIT_SHIFT)
664 #define PABIT_DEFAULT 0x2f
674 #define GR32_DEFAULT 0
676 #define MCSR0_PRID 0x14C010
678 #define LOONGARCH_CSR_MCSR1 0xc1 /* CPUCFG2 and CPUCFG3 */
735 #define MCSR1_FP_SHIFT 0
738 #define LOONGARCH_CSR_MCSR2 0xc2 /* CPUCFG4 and CPUCFG5 */
741 #define MCSR2_CCDIV (_ULCAST_(0xffff) << MCSR2_CCDIV_SHIFT)
744 #define MCSR2_CCMUL (_ULCAST_(0xffff) << MCSR2_CCMUL_SHIFT)
746 #define MCSR2_CCFREQ (_ULCAST_(0xffffffff))
747 #define CCFREQ_DEFAULT 0x5f5e100 /* 100MHz */
749 #define LOONGARCH_CSR_MCSR3 0xc3 /* CPUCFG6 */
754 #define MCSR3_PMBITS (_ULCAST_(0x3f) << MCSR3_PMBITS_SHIFT)
755 #define PMBITS_DEFAULT 0x40
758 #define MCSR3_PMNUM (_ULCAST_(0xf) << MCSR3_PMNUM_SHIFT)
761 #define MCSR3_PAMVER (_ULCAST_(0x7) << MCSR3_PAMVER_SHIFT)
762 #define MCSR3_PMP_SHIFT 0
765 #define LOONGARCH_CSR_MCSR8 0xc8 /* CPUCFG16 and CPUCFG17 */
768 #define MCSR8_L1I_SIZE (_ULCAST_(0x7f) << MCSR8_L1I_SIZE_SHIFT)
771 #define MCSR8_L1I_IDX (_ULCAST_(0xff) << MCSR8_L1I_IDX_SHIFT)
774 #define MCSR8_L1I_WAY (_ULCAST_(0xffff) << MCSR8_L1I_WAY_SHIFT)
807 #define MCSR8_L1IUPRE_SHIFT 0
810 #define LOONGARCH_CSR_MCSR9 0xc9 /* CPUCFG18 and CPUCFG19 */
813 #define MCSR9_L2U_SIZE (_ULCAST_(0x7f) << MCSR9_L2U_SIZE_SHIFT)
816 #define MCSR9_L2U_IDX (_ULCAST_(0xff) << MCSR9_IDX_LOG_SHIFT)
819 #define MCSR9_L2U_WAY (_ULCAST_(0xffff) << MCSR9_L2U_WAY_SHIFT)
822 #define MCSR9_L1D_SIZE (_ULCAST_(0x7f) << MCSR9_L1D_SIZE_SHIFT)
825 #define MCSR9_L1D_IDX (_ULCAST_(0xff) << MCSR9_L1D_IDX_SHIFT)
826 #define MCSR9_L1D_WAY_SHIFT 0
828 #define MCSR9_L1D_WAY (_ULCAST_(0xffff) << MCSR9_L1D_WAY_SHIFT)
830 #define LOONGARCH_CSR_MCSR10 0xca /* CPUCFG20 */
833 #define MCSR10_L3U_SIZE (_ULCAST_(0x7f) << MCSR10_L3U_SIZE_SHIFT)
836 #define MCSR10_L3U_IDX (_ULCAST_(0xff) << MCSR10_L3U_IDX_SHIFT)
837 #define MCSR10_L3U_WAY_SHIFT 0
839 #define MCSR10_L3U_WAY (_ULCAST_(0xffff) << MCSR10_L3U_WAY_SHIFT)
841 #define LOONGARCH_CSR_MCSR24 0xf0 /* cpucfg48 */
848 #define MCSR24_MCSRLOCK_SHIFT 0
852 #define LOONGARCH_CSR_UCAWIN 0x100
853 #define LOONGARCH_CSR_UCAWIN0_LO 0x102
854 #define LOONGARCH_CSR_UCAWIN0_HI 0x103
855 #define LOONGARCH_CSR_UCAWIN1_LO 0x104
856 #define LOONGARCH_CSR_UCAWIN1_HI 0x105
857 #define LOONGARCH_CSR_UCAWIN2_LO 0x106
858 #define LOONGARCH_CSR_UCAWIN2_HI 0x107
859 #define LOONGARCH_CSR_UCAWIN3_LO 0x108
860 #define LOONGARCH_CSR_UCAWIN3_HI 0x109
863 #define LOONGARCH_CSR_DMWIN0 0x180 /* 64 direct map win0: MEM & IF */
864 #define LOONGARCH_CSR_DMWIN1 0x181 /* 64 direct map win1: MEM & IF */
865 #define LOONGARCH_CSR_DMWIN2 0x182 /* 64 direct map win2: MEM */
866 #define LOONGARCH_CSR_DMWIN3 0x183 /* 64 direct map win3: MEM */
868 /* Direct Map window 0/1 */
869 #define CSR_DMW0_PLV0 _CONST64_(1 << 0)
870 #define CSR_DMW0_VSEG _CONST64_(0x8000)
874 #define CSR_DMW1_PLV0 _CONST64_(1 << 0)
876 #define CSR_DMW1_VSEG _CONST64_(0x9000)
881 #define LOONGARCH_CSR_PERFCTRL0 0x200 /* 32 perf event 0 config */
882 #define LOONGARCH_CSR_PERFCNTR0 0x201 /* 64 perf event 0 count value */
883 #define LOONGARCH_CSR_PERFCTRL1 0x202 /* 32 perf event 1 config */
884 #define LOONGARCH_CSR_PERFCNTR1 0x203 /* 64 perf event 1 count value */
885 #define LOONGARCH_CSR_PERFCTRL2 0x204 /* 32 perf event 2 config */
886 #define LOONGARCH_CSR_PERFCNTR2 0x205 /* 64 perf event 2 count value */
887 #define LOONGARCH_CSR_PERFCTRL3 0x206 /* 32 perf event 3 config */
888 #define LOONGARCH_CSR_PERFCNTR3 0x207 /* 64 perf event 3 count value */
894 #define CSR_PERFCTRL_EVENT 0x3ff
897 #define LOONGARCH_CSR_MWPC 0x300 /* data breakpoint config */
898 #define LOONGARCH_CSR_MWPS 0x301 /* data breakpoint status */
900 #define LOONGARCH_CSR_DB0ADDR 0x310 /* data breakpoint 0 address */
901 #define LOONGARCH_CSR_DB0MASK 0x311 /* data breakpoint 0 mask */
902 #define LOONGARCH_CSR_DB0CTRL 0x312 /* data breakpoint 0 control */
903 #define LOONGARCH_CSR_DB0ASID 0x313 /* data breakpoint 0 asid */
905 #define LOONGARCH_CSR_DB1ADDR 0x318 /* data breakpoint 1 address */
906 #define LOONGARCH_CSR_DB1MASK 0x319 /* data breakpoint 1 mask */
907 #define LOONGARCH_CSR_DB1CTRL 0x31a /* data breakpoint 1 control */
908 #define LOONGARCH_CSR_DB1ASID 0x31b /* data breakpoint 1 asid */
910 #define LOONGARCH_CSR_DB2ADDR 0x320 /* data breakpoint 2 address */
911 #define LOONGARCH_CSR_DB2MASK 0x321 /* data breakpoint 2 mask */
912 #define LOONGARCH_CSR_DB2CTRL 0x322 /* data breakpoint 2 control */
913 #define LOONGARCH_CSR_DB2ASID 0x323 /* data breakpoint 2 asid */
915 #define LOONGARCH_CSR_DB3ADDR 0x328 /* data breakpoint 3 address */
916 #define LOONGARCH_CSR_DB3MASK 0x329 /* data breakpoint 3 mask */
917 #define LOONGARCH_CSR_DB3CTRL 0x32a /* data breakpoint 3 control */
918 #define LOONGARCH_CSR_DB3ASID 0x32b /* data breakpoint 3 asid */
920 #define LOONGARCH_CSR_DB4ADDR 0x330 /* data breakpoint 4 address */
921 #define LOONGARCH_CSR_DB4MASK 0x331 /* data breakpoint 4 maks */
922 #define LOONGARCH_CSR_DB4CTRL 0x332 /* data breakpoint 4 control */
923 #define LOONGARCH_CSR_DB4ASID 0x333 /* data breakpoint 4 asid */
925 #define LOONGARCH_CSR_DB5ADDR 0x338 /* data breakpoint 5 address */
926 #define LOONGARCH_CSR_DB5MASK 0x339 /* data breakpoint 5 mask */
927 #define LOONGARCH_CSR_DB5CTRL 0x33a /* data breakpoint 5 control */
928 #define LOONGARCH_CSR_DB5ASID 0x33b /* data breakpoint 5 asid */
930 #define LOONGARCH_CSR_DB6ADDR 0x340 /* data breakpoint 6 address */
931 #define LOONGARCH_CSR_DB6MASK 0x341 /* data breakpoint 6 mask */
932 #define LOONGARCH_CSR_DB6CTRL 0x342 /* data breakpoint 6 control */
933 #define LOONGARCH_CSR_DB6ASID 0x343 /* data breakpoint 6 asid */
935 #define LOONGARCH_CSR_DB7ADDR 0x348 /* data breakpoint 7 address */
936 #define LOONGARCH_CSR_DB7MASK 0x349 /* data breakpoint 7 mask */
937 #define LOONGARCH_CSR_DB7CTRL 0x34a /* data breakpoint 7 control */
938 #define LOONGARCH_CSR_DB7ASID 0x34b /* data breakpoint 7 asid */
940 #define LOONGARCH_CSR_FWPC 0x380 /* instruction breakpoint config */
941 #define LOONGARCH_CSR_FWPS 0x381 /* instruction breakpoint status */
943 #define LOONGARCH_CSR_IB0ADDR 0x390 /* inst breakpoint 0 address */
944 #define LOONGARCH_CSR_IB0MASK 0x391 /* inst breakpoint 0 mask */
945 #define LOONGARCH_CSR_IB0CTRL 0x392 /* inst breakpoint 0 control */
946 #define LOONGARCH_CSR_IB0ASID 0x393 /* inst breakpoint 0 asid */
948 #define LOONGARCH_CSR_IB1ADDR 0x398 /* inst breakpoint 1 address */
949 #define LOONGARCH_CSR_IB1MASK 0x399 /* inst breakpoint 1 mask */
950 #define LOONGARCH_CSR_IB1CTRL 0x39a /* inst breakpoint 1 control */
951 #define LOONGARCH_CSR_IB1ASID 0x39b /* inst breakpoint 1 asid */
953 #define LOONGARCH_CSR_IB2ADDR 0x3a0 /* inst breakpoint 2 address */
954 #define LOONGARCH_CSR_IB2MASK 0x3a1 /* inst breakpoint 2 mask */
955 #define LOONGARCH_CSR_IB2CTRL 0x3a2 /* inst breakpoint 2 control */
956 #define LOONGARCH_CSR_IB2ASID 0x3a3 /* inst breakpoint 2 asid */
958 #define LOONGARCH_CSR_IB3ADDR 0x3a8 /* inst breakpoint 3 address */
959 #define LOONGARCH_CSR_IB3MASK 0x3a9 /* breakpoint 3 mask */
960 #define LOONGARCH_CSR_IB3CTRL 0x3aa /* inst breakpoint 3 control */
961 #define LOONGARCH_CSR_IB3ASID 0x3ab /* inst breakpoint 3 asid */
963 #define LOONGARCH_CSR_IB4ADDR 0x3b0 /* inst breakpoint 4 address */
964 #define LOONGARCH_CSR_IB4MASK 0x3b1 /* inst breakpoint 4 mask */
965 #define LOONGARCH_CSR_IB4CTRL 0x3b2 /* inst breakpoint 4 control */
966 #define LOONGARCH_CSR_IB4ASID 0x3b3 /* inst breakpoint 4 asid */
968 #define LOONGARCH_CSR_IB5ADDR 0x3b8 /* inst breakpoint 5 address */
969 #define LOONGARCH_CSR_IB5MASK 0x3b9 /* inst breakpoint 5 mask */
970 #define LOONGARCH_CSR_IB5CTRL 0x3ba /* inst breakpoint 5 control */
971 #define LOONGARCH_CSR_IB5ASID 0x3bb /* inst breakpoint 5 asid */
973 #define LOONGARCH_CSR_IB6ADDR 0x3c0 /* inst breakpoint 6 address */
974 #define LOONGARCH_CSR_IB6MASK 0x3c1 /* inst breakpoint 6 mask */
975 #define LOONGARCH_CSR_IB6CTRL 0x3c2 /* inst breakpoint 6 control */
976 #define LOONGARCH_CSR_IB6ASID 0x3c3 /* inst breakpoint 6 asid */
978 #define LOONGARCH_CSR_IB7ADDR 0x3c8 /* inst breakpoint 7 address */
979 #define LOONGARCH_CSR_IB7MASK 0x3c9 /* inst breakpoint 7 mask */
980 #define LOONGARCH_CSR_IB7CTRL 0x3ca /* inst breakpoint 7 control */
981 #define LOONGARCH_CSR_IB7ASID 0x3cb /* inst breakpoint 7 asid */
983 #define LOONGARCH_CSR_DEBUG 0x500 /* debug config */
984 #define LOONGARCH_CSR_DERA 0x501 /* debug era */
985 #define LOONGARCH_CSR_DESAVE 0x502 /* debug save */
993 #define ECFG0_IM 0x00001fff
994 #define ECFGB_SIP0 0
1022 #define ESTATF_IP 0x00003fff
1024 #define LOONGARCH_IOCSR_FEATURES 0x8
1025 #define IOCSRF_TEMP BIT_ULL(0)
1037 #define LOONGARCH_IOCSR_VENDOR 0x10
1039 #define LOONGARCH_IOCSR_CPUNAME 0x20
1041 #define LOONGARCH_IOCSR_NODECNT 0x408
1043 #define LOONGARCH_IOCSR_MISC_FUNC 0x420
1047 #define LOONGARCH_IOCSR_CPUTEMP 0x428
1050 #define LOONGARCH_IOCSR_IPI_STATUS 0x1000
1051 #define LOONGARCH_IOCSR_IPI_EN 0x1004
1052 #define LOONGARCH_IOCSR_IPI_SET 0x1008
1053 #define LOONGARCH_IOCSR_IPI_CLEAR 0x100c
1054 #define LOONGARCH_IOCSR_MBUF0 0x1020
1055 #define LOONGARCH_IOCSR_MBUF1 0x1028
1056 #define LOONGARCH_IOCSR_MBUF2 0x1030
1057 #define LOONGARCH_IOCSR_MBUF3 0x1038
1059 #define LOONGARCH_IOCSR_IPI_SEND 0x1040
1060 #define IOCSR_IPI_SEND_IP_SHIFT 0
1064 #define LOONGARCH_IOCSR_MBUF_SEND 0x1048
1071 #define IOCSR_MBUF_SEND_H32_MASK 0xFFFFFFFF00000000ULL
1073 #define LOONGARCH_IOCSR_ANY_SEND 0x1158
1078 #define IOCSR_ANY_SEND_H32_MASK 0xFFFFFFFF00000000ULL
1081 #define LOONGARCH_IOCSR_TIMER_CFG 0x1060
1082 #define LOONGARCH_IOCSR_TIMER_TICK 0x1070
1086 #define IOCSR_TIMER_MASK 0x0ffffffffffffULL
1087 #define IOCSR_TIMER_INITVAL_RST (_ULCAST_(0xffff) << 48)
1089 #define LOONGARCH_IOCSR_EXTIOI_NODEMAP_BASE 0x14a0
1090 #define LOONGARCH_IOCSR_EXTIOI_IPMAP_BASE 0x14c0
1091 #define LOONGARCH_IOCSR_EXTIOI_EN_BASE 0x1600
1092 #define LOONGARCH_IOCSR_EXTIOI_BOUNCE_BASE 0x1680
1093 #define LOONGARCH_IOCSR_EXTIOI_ISR_BASE 0x1800
1094 #define LOONGARCH_IOCSR_EXTIOI_ROUTE_BASE 0x1c00
1101 u64 val = 0; in drdtime()
1104 "rdtime.d %0, $zero\n\t" in drdtime()
1119 uint64_t val = 0; in csr_any_send()
1262 #define ENTRYLO_V (_ULCAST_(1) << 0)
1273 #define PS_4K 0x0000000c
1274 #define PS_8K 0x0000000d
1275 #define PS_16K 0x0000000e
1276 #define PS_32K 0x0000000f
1277 #define PS_64K 0x00000010
1278 #define PS_128K 0x00000011
1279 #define PS_256K 0x00000012
1280 #define PS_512K 0x00000013
1281 #define PS_1M 0x00000014
1282 #define PS_2M 0x00000015
1283 #define PS_4M 0x00000016
1284 #define PS_8M 0x00000017
1285 #define PS_16M 0x00000018
1286 #define PS_32M 0x00000019
1287 #define PS_64M 0x0000001a
1288 #define PS_128M 0x0000001b
1289 #define PS_256M 0x0000001c
1290 #define PS_512M 0x0000001d
1291 #define PS_1G 0x0000001e
1316 #define EXCCODE_RSV 0 /* Reserved */
1325 #define EXSUBCODE_ADEF 0 /* Fetch Instruction */
1337 #define EXCSUBCODE_FPE 0 /* Floating Point Exception */
1340 #define EXCSUBCODE_WPEF 0 /* ... on Instruction Fetch */
1347 #define EXCSUBCODE_GCSC 0 /* Software caused */
1352 #define INT_SWI0 0 /* Software Interrupts */
1386 #define FPU_CSR_RSVD 0xe0e0fce0
1393 #define FPU_CSR_ALL_X 0x1f000000
1394 #define FPU_CSR_INV_X 0x10000000
1395 #define FPU_CSR_DIV_X 0x08000000
1396 #define FPU_CSR_OVF_X 0x04000000
1397 #define FPU_CSR_UDF_X 0x02000000
1398 #define FPU_CSR_INE_X 0x01000000
1400 #define FPU_CSR_ALL_S 0x001f0000
1401 #define FPU_CSR_INV_S 0x00100000
1402 #define FPU_CSR_DIV_S 0x00080000
1403 #define FPU_CSR_OVF_S 0x00040000
1404 #define FPU_CSR_UDF_S 0x00020000
1405 #define FPU_CSR_INE_S 0x00010000
1407 #define FPU_CSR_ALL_E 0x0000001f
1408 #define FPU_CSR_INV_E 0x00000010
1409 #define FPU_CSR_DIV_E 0x00000008
1410 #define FPU_CSR_OVF_E 0x00000004
1411 #define FPU_CSR_UDF_E 0x00000002
1412 #define FPU_CSR_INE_E 0x00000001
1415 #define FPU_CSR_RM 0x300
1416 #define FPU_CSR_RN 0x000 /* nearest */
1417 #define FPU_CSR_RZ 0x100 /* towards zero */
1418 #define FPU_CSR_RU 0x200 /* towards +Infinity */
1419 #define FPU_CSR_RD 0x300 /* towards -Infinity */
1422 #define FPU_CSR_TM_SHIFT 0x6
1430 " movfcsr2gr %0, "__stringify(source)" \n" \
1438 " movgr2fcsr "__stringify(dest)", %0 \n" \
1440 } while (0)