Lines Matching +full:enum +full:- +full:name
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
36 enum reg0i15_op {
40 enum reg0i26_op {
45 enum reg1i20_op {
54 enum reg1i21_op {
61 enum reg2_op {
80 enum reg2i5_op {
86 enum reg2i6_op {
92 enum reg2i12_op {
116 enum reg2i14_op {
127 enum reg2i16_op {
137 enum reg2bstrd_op {
142 enum reg3_op {
252 enum reg3sa2_op {
373 enum loongarch_gpr {
412 return val & (1UL << (bit - 1)); in is_imm_negative()
417 return ip->reg0i15_format.opcode == break_op; in is_break_ins()
422 return ip->reg1i20_format.opcode >= pcaddi_op && in is_pc_ins()
423 ip->reg1i20_format.opcode <= pcaddu18i_op; in is_pc_ins()
428 return ip->reg1i21_format.opcode >= beqz_op && in is_branch_ins()
429 ip->reg1i21_format.opcode <= bgeu_op; in is_branch_ins()
435 return ip->reg2i12_format.opcode == std_op && in is_ra_save_ins()
436 ip->reg2i12_format.rj == LOONGARCH_GPR_SP && in is_ra_save_ins()
437 ip->reg2i12_format.rd == LOONGARCH_GPR_RA && in is_ra_save_ins()
438 !is_imm12_negative(ip->reg2i12_format.immediate); in is_ra_save_ins()
443 /* addi.d $sp, $sp, -imm */ in is_stack_alloc_ins()
444 return ip->reg2i12_format.opcode == addid_op && in is_stack_alloc_ins()
445 ip->reg2i12_format.rj == LOONGARCH_GPR_SP && in is_stack_alloc_ins()
446 ip->reg2i12_format.rd == LOONGARCH_GPR_SP && in is_stack_alloc_ins()
447 is_imm12_negative(ip->reg2i12_format.immediate); in is_stack_alloc_ins()
452 switch (ip->reg0i26_format.opcode) { in is_self_loop_ins()
455 if (ip->reg0i26_format.immediate_l == 0 in is_self_loop_ins()
456 && ip->reg0i26_format.immediate_h == 0) in is_self_loop_ins()
460 switch (ip->reg1i21_format.opcode) { in is_self_loop_ins()
464 if (ip->reg1i21_format.immediate_l == 0 in is_self_loop_ins()
465 && ip->reg1i21_format.immediate_h == 0) in is_self_loop_ins()
469 switch (ip->reg2i16_format.opcode) { in is_self_loop_ins()
476 if (ip->reg2i16_format.immediate == 0) in is_self_loop_ins()
480 if (regs->regs[ip->reg2i16_format.rj] + in is_self_loop_ins()
481 ((unsigned long)ip->reg2i16_format.immediate << 2) == (unsigned long)ip) in is_self_loop_ins()
505 u32 larch_insn_gen_or(enum loongarch_gpr rd, enum loongarch_gpr rj, enum loongarch_gpr rk);
506 u32 larch_insn_gen_move(enum loongarch_gpr rd, enum loongarch_gpr rj);
508 u32 larch_insn_gen_lu12iw(enum loongarch_gpr rd, int imm);
509 u32 larch_insn_gen_lu32id(enum loongarch_gpr rd, int imm);
510 u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
511 u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
515 return -(1L << (bit - 1)) <= val && val < (1L << (bit - 1)); in signed_imm_check()
523 #define DEF_EMIT_REG0I15_FORMAT(NAME, OP) \ argument
524 static inline void emit_##NAME(union loongarch_instruction *insn, \
527 insn->reg0i15_format.opcode = OP; \
528 insn->reg0i15_format.immediate = imm; \
533 #define DEF_EMIT_REG0I26_FORMAT(NAME, OP) \ argument
534 static inline void emit_##NAME(union loongarch_instruction *insn, \
543 insn->reg0i26_format.opcode = OP; \
544 insn->reg0i26_format.immediate_l = immediate_l; \
545 insn->reg0i26_format.immediate_h = immediate_h; \
551 #define DEF_EMIT_REG1I20_FORMAT(NAME, OP) \ argument
552 static inline void emit_##NAME(union loongarch_instruction *insn, \
553 enum loongarch_gpr rd, int imm) \
555 insn->reg1i20_format.opcode = OP; \
556 insn->reg1i20_format.immediate = imm; \
557 insn->reg1i20_format.rd = rd; \
564 #define DEF_EMIT_REG2_FORMAT(NAME, OP) \ argument
565 static inline void emit_##NAME(union loongarch_instruction *insn, \
566 enum loongarch_gpr rd, \
567 enum loongarch_gpr rj) \
569 insn->reg2_format.opcode = OP; \
570 insn->reg2_format.rd = rd; \
571 insn->reg2_format.rj = rj; \
580 #define DEF_EMIT_REG2I5_FORMAT(NAME, OP) \ argument
581 static inline void emit_##NAME(union loongarch_instruction *insn, \
582 enum loongarch_gpr rd, \
583 enum loongarch_gpr rj, \
586 insn->reg2i5_format.opcode = OP; \
587 insn->reg2i5_format.immediate = imm; \
588 insn->reg2i5_format.rd = rd; \
589 insn->reg2i5_format.rj = rj; \
596 #define DEF_EMIT_REG2I6_FORMAT(NAME, OP) \ argument
597 static inline void emit_##NAME(union loongarch_instruction *insn, \
598 enum loongarch_gpr rd, \
599 enum loongarch_gpr rj, \
602 insn->reg2i6_format.opcode = OP; \
603 insn->reg2i6_format.immediate = imm; \
604 insn->reg2i6_format.rd = rd; \
605 insn->reg2i6_format.rj = rj; \
612 #define DEF_EMIT_REG2I12_FORMAT(NAME, OP) \ argument
613 static inline void emit_##NAME(union loongarch_instruction *insn, \
614 enum loongarch_gpr rd, \
615 enum loongarch_gpr rj, \
618 insn->reg2i12_format.opcode = OP; \
619 insn->reg2i12_format.immediate = imm; \
620 insn->reg2i12_format.rd = rd; \
621 insn->reg2i12_format.rj = rj; \
642 #define DEF_EMIT_REG2I14_FORMAT(NAME, OP) \ argument
643 static inline void emit_##NAME(union loongarch_instruction *insn, \
644 enum loongarch_gpr rd, \
645 enum loongarch_gpr rj, \
648 insn->reg2i14_format.opcode = OP; \
649 insn->reg2i14_format.immediate = imm; \
650 insn->reg2i14_format.rd = rd; \
651 insn->reg2i14_format.rj = rj; \
663 #define DEF_EMIT_REG2I16_FORMAT(NAME, OP) \ argument
664 static inline void emit_##NAME(union loongarch_instruction *insn, \
665 enum loongarch_gpr rj, \
666 enum loongarch_gpr rd, \
669 insn->reg2i16_format.opcode = OP; \
670 insn->reg2i16_format.immediate = offset; \
671 insn->reg2i16_format.rj = rj; \
672 insn->reg2i16_format.rd = rd; \
683 #define DEF_EMIT_REG2BSTRD_FORMAT(NAME, OP) \ argument
684 static inline void emit_##NAME(union loongarch_instruction *insn, \
685 enum loongarch_gpr rd, \
686 enum loongarch_gpr rj, \
690 insn->reg2bstrd_format.opcode = OP; \
691 insn->reg2bstrd_format.msbd = msbd; \
692 insn->reg2bstrd_format.lsbd = lsbd; \
693 insn->reg2bstrd_format.rj = rj; \
694 insn->reg2bstrd_format.rd = rd; \
699 #define DEF_EMIT_REG3_FORMAT(NAME, OP) \ argument
700 static inline void emit_##NAME(union loongarch_instruction *insn, \
701 enum loongarch_gpr rd, \
702 enum loongarch_gpr rj, \
703 enum loongarch_gpr rk) \
705 insn->reg3_format.opcode = OP; \
706 insn->reg3_format.rd = rd; \
707 insn->reg3_format.rj = rj; \
708 insn->reg3_format.rk = rk; \
750 #define DEF_EMIT_REG3SA2_FORMAT(NAME, OP) \ argument
751 static inline void emit_##NAME(union loongarch_instruction *insn, \
752 enum loongarch_gpr rd, \
753 enum loongarch_gpr rj, \
754 enum loongarch_gpr rk, \
757 insn->reg3sa2_format.opcode = OP; \
758 insn->reg3sa2_format.immediate = imm; \
759 insn->reg3sa2_format.rd = rd; \
760 insn->reg3sa2_format.rj = rj; \
761 insn->reg3sa2_format.rk = rk; \