Lines Matching +full:3 +full:- +full:7
1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
96 #define PSTATE_UAO pstate_field(0, 3)
97 #define PSTATE_SSBS pstate_field(3, 1)
98 #define PSTATE_DIT pstate_field(3, 2)
99 #define PSTATE_TCO pstate_field(3, 4)
113 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
115 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31)
117 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
118 #define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4)
119 #define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6)
120 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
121 #define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4)
122 #define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6)
123 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
124 #define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4)
125 #define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6)
127 #define SYS_IC_IALLUIS sys_insn(1, 0, 7, 1, 0)
128 #define SYS_IC_IALLU sys_insn(1, 0, 7, 5, 0)
129 #define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1)
131 #define SYS_DC_IVAC sys_insn(1, 0, 7, 6, 1)
132 #define SYS_DC_IGVAC sys_insn(1, 0, 7, 6, 3)
133 #define SYS_DC_IGDVAC sys_insn(1, 0, 7, 6, 5)
135 #define SYS_DC_CVAC sys_insn(1, 3, 7, 10, 1)
136 #define SYS_DC_CGVAC sys_insn(1, 3, 7, 10, 3)
137 #define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5)
139 #define SYS_DC_CVAU sys_insn(1, 3, 7, 11, 1)
141 #define SYS_DC_CVAP sys_insn(1, 3, 7, 12, 1)
142 #define SYS_DC_CGVAP sys_insn(1, 3, 7, 12, 3)
143 #define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5)
145 #define SYS_DC_CVADP sys_insn(1, 3, 7, 13, 1)
146 #define SYS_DC_CGVADP sys_insn(1, 3, 7, 13, 3)
147 #define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5)
149 #define SYS_DC_CIVAC sys_insn(1, 3, 7, 14, 1)
150 #define SYS_DC_CIGVAC sys_insn(1, 3, 7, 14, 3)
151 #define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5)
154 #define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1)
155 #define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3)
156 #define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4)
164 #include "asm/sysreg-defs.h"
170 #define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3)
171 #define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3)
172 #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3)
177 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
181 #define OSLSR_EL1_OSLM_MASK (BIT(3) | BIT(0))
183 #define OSLSR_EL1_OSLM_IMPLEMENTED BIT(3)
186 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
188 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
189 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
190 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
191 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
192 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
193 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
194 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
195 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
209 #define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
210 #define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
211 #define SYS_TRCACVR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))
212 #define SYS_TRCAUTHSTATUS sys_reg(2, 1, 7, 14, 6)
216 #define SYS_TRCCIDCCTLR0 sys_reg(2, 1, 3, 0, 2)
217 #define SYS_TRCCIDCCTLR1 sys_reg(2, 1, 3, 1, 2)
218 #define SYS_TRCCIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 0)
219 #define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6)
220 #define SYS_TRCCLAIMSET sys_reg(2, 1, 7, 8, 6)
221 #define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5)
222 #define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5)
223 #define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5)
225 #define SYS_TRCDEVARCH sys_reg(2, 1, 7, 15, 6)
226 #define SYS_TRCDEVID sys_reg(2, 1, 7, 2, 7)
229 #define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4)
230 #define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7)
232 #define SYS_TRCIDR11 sys_reg(2, 1, 0, 3, 6)
235 #define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7)
236 #define SYS_TRCIDR2 sys_reg(2, 1, 0, 10, 7)
237 #define SYS_TRCIDR3 sys_reg(2, 1, 0, 11, 7)
238 #define SYS_TRCIDR4 sys_reg(2, 1, 0, 12, 7)
239 #define SYS_TRCIDR5 sys_reg(2, 1, 0, 13, 7)
240 #define SYS_TRCIDR6 sys_reg(2, 1, 0, 14, 7)
241 #define SYS_TRCIDR7 sys_reg(2, 1, 0, 15, 7)
244 #define SYS_TRCIMSPEC(m) sys_reg(2, 1, 0, (m & 7), 7)
251 #define SYS_TRCSEQEVR(m) sys_reg(2, 1, 0, (m & 3), 4)
253 #define SYS_TRCSEQSTR sys_reg(2, 1, 0, 7, 4)
254 #define SYS_TRCSSCCR(m) sys_reg(2, 1, 1, (m & 7), 2)
255 #define SYS_TRCSSCSR(m) sys_reg(2, 1, 1, (8 | (m & 7)), 2)
256 #define SYS_TRCSSPCICR(m) sys_reg(2, 1, 1, (m & 7), 3)
258 #define SYS_TRCSTATR sys_reg(2, 1, 0, 3, 0)
264 #define SYS_TRCVIPCSSCTLR sys_reg(2, 1, 0, 3, 2)
266 #define SYS_TRCVMIDCCTLR0 sys_reg(2, 1, 3, 2, 2)
267 #define SYS_TRCVMIDCCTLR1 sys_reg(2, 1, 3, 3, 2)
268 #define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1)
275 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
276 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
277 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
279 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
280 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
281 #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
283 #define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
285 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
287 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
288 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1)
289 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2)
290 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3)
292 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0)
293 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1)
294 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2)
295 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3)
297 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0)
298 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1)
300 #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0)
301 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1)
303 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
305 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
306 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
307 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
309 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
310 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
311 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
312 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
313 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
314 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
315 #define SYS_ERXPFGF_EL1 sys_reg(3, 0, 5, 4, 4)
316 #define SYS_ERXPFGCTL_EL1 sys_reg(3, 0, 5, 4, 5)
317 #define SYS_ERXPFGCDN_EL1 sys_reg(3, 0, 5, 4, 6)
318 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
319 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
320 #define SYS_ERXMISC2_EL1 sys_reg(3, 0, 5, 5, 2)
321 #define SYS_ERXMISC3_EL1 sys_reg(3, 0, 5, 5, 3)
322 #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
323 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
325 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
353 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
354 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
356 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
358 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
359 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
361 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
362 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
364 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
365 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
366 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
367 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
368 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
372 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3)
373 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
377 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3)
378 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
379 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
380 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
381 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
382 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
383 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
384 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
385 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
386 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
387 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
388 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
389 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
390 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
392 #define SYS_ACCDATA_EL1 sys_reg(3, 0, 13, 0, 5)
394 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
396 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
398 #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
399 #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
401 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
402 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
403 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
404 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
405 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
406 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
407 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
408 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
409 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
410 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
411 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
412 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
413 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
415 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
416 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
417 #define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5)
419 #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7)
422 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2))
426 #define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3)
429 #define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0)
430 #define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1)
435 * Counter: 11 011 1101 010:n<3> n<2:0>
436 * Type: 11 011 1101 011:n<3> n<2:0>
437 * n: 0-15
441 * Counter: 11 011 1101 110:n<3> n<2:0>
442 * Type: 11 011 1101 111:n<3> n<2:0>
443 * n: 0-15
446 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
447 #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
448 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
449 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
455 #define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3)
457 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
459 #define SYS_CNTPCT_EL0 sys_reg(3, 3, 14, 0, 1)
460 #define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5)
461 #define SYS_CNTVCTSS_EL0 sys_reg(3, 3, 14, 0, 6)
463 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
464 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
465 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
467 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1)
468 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2)
477 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
478 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
479 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
480 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
482 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
484 #define SYS_VPIDR_EL2 sys_reg(3, 4, 0, 0, 0)
485 #define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5)
487 #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
488 #define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1)
489 #define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3)
490 #define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0)
491 #define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
492 #define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
493 #define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3)
494 #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
496 #define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0)
497 #define SYS_TTBR1_EL2 sys_reg(3, 4, 2, 0, 1)
498 #define SYS_TCR_EL2 sys_reg(3, 4, 2, 0, 2)
499 #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0)
500 #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
502 #define SYS_TRFCR_EL2 sys_reg(3, 4, 1, 2, 1)
503 #define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0)
504 #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
505 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
506 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
507 #define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0)
508 #define SYS_SPSR_irq sys_reg(3, 4, 4, 3, 0)
509 #define SYS_SPSR_abt sys_reg(3, 4, 4, 3, 1)
510 #define SYS_SPSR_und sys_reg(3, 4, 4, 3, 2)
511 #define SYS_SPSR_fiq sys_reg(3, 4, 4, 3, 3)
512 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
513 #define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0)
514 #define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1)
515 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
516 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
517 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
518 #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
520 #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
521 #define SYS_HPFAR_EL2 sys_reg(3, 4, 6, 0, 4)
523 #define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0)
524 #define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0)
525 #define SYS_MPAMHCR_EL2 sys_reg(3, 4, 10, 4, 0)
526 #define SYS_MPAMVPMV_EL2 sys_reg(3, 4, 10, 4, 1)
527 #define SYS_MPAM2_EL2 sys_reg(3, 4, 10, 5, 0)
528 #define __SYS__MPAMVPMx_EL2(x) sys_reg(3, 4, 10, 6, x)
532 #define SYS_MPAMVPM3_EL2 __SYS__MPAMVPMx_EL2(3)
536 #define SYS_MPAMVPM7_EL2 __SYS__MPAMVPMx_EL2(7)
538 #define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0)
539 #define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1)
540 #define SYS_RMR_EL2 sys_reg(3, 4, 12, 0, 2)
541 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
542 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
546 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
548 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
552 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
554 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
555 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
556 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
557 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
558 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
559 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
560 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
561 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
563 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
567 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
571 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7)
573 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
577 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
581 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
583 #define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1)
584 #define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2)
585 #define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7)
588 #define __AMEV_CRm(n, m) (n | ((m & 0x8) >> 3))
589 #define __SYS__AMEVCNTVOFF0n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m))
591 #define __SYS__AMEVCNTVOFF1n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m))
594 #define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3)
595 #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0)
596 #define SYS_CNTHP_TVAL_EL2 sys_reg(3, 4, 14, 2, 0)
597 #define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1)
598 #define SYS_CNTHP_CVAL_EL2 sys_reg(3, 4, 14, 2, 2)
599 #define SYS_CNTHV_TVAL_EL2 sys_reg(3, 4, 14, 3, 0)
600 #define SYS_CNTHV_CTL_EL2 sys_reg(3, 4, 14, 3, 1)
601 #define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2)
605 #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
606 #define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
607 #define SYS_SCTLR2_EL12 sys_reg(3, 5, 1, 0, 3)
608 #define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0)
609 #define SYS_TRFCR_EL12 sys_reg(3, 5, 1, 2, 1)
610 #define SYS_SMCR_EL12 sys_reg(3, 5, 1, 2, 6)
611 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
612 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
613 #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
614 #define SYS_TCR2_EL12 sys_reg(3, 5, 2, 0, 3)
615 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
616 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
617 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
618 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
619 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
620 #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
621 #define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0)
622 #define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0)
623 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
624 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
625 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
626 #define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1)
627 #define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7)
628 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
629 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
630 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
631 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
632 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
633 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
634 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
636 #define SYS_SP_EL2 sys_reg(3, 6, 4, 1, 0)
640 #define AT_CRn 7
645 #define OP_AT_S1E0W sys_insn(AT_Op0, 0, AT_CRn, 8, 3)
654 #define OP_AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7)
660 #define OP_TLBI_VAAE1OS sys_insn(1, 0, 8, 1, 3)
662 #define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7)
664 #define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3)
666 #define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7)
667 #define OP_TLBI_VMALLE1IS sys_insn(1, 0, 8, 3, 0)
668 #define OP_TLBI_VAE1IS sys_insn(1, 0, 8, 3, 1)
669 #define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2)
670 #define OP_TLBI_VAAE1IS sys_insn(1, 0, 8, 3, 3)
671 #define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5)
672 #define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7)
674 #define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3)
676 #define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7)
678 #define OP_TLBI_RVAAE1 sys_insn(1, 0, 8, 6, 3)
680 #define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7)
681 #define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0)
682 #define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1)
683 #define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2)
684 #define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3)
685 #define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5)
686 #define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7)
690 #define OP_TLBI_VAAE1OSNXS sys_insn(1, 0, 9, 1, 3)
692 #define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7)
694 #define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3)
696 #define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7)
697 #define OP_TLBI_VMALLE1ISNXS sys_insn(1, 0, 9, 3, 0)
698 #define OP_TLBI_VAE1ISNXS sys_insn(1, 0, 9, 3, 1)
699 #define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2)
700 #define OP_TLBI_VAAE1ISNXS sys_insn(1, 0, 9, 3, 3)
701 #define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)
702 #define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7)
704 #define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)
706 #define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)
708 #define OP_TLBI_RVAAE1NXS sys_insn(1, 0, 9, 6, 3)
710 #define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7)
711 #define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0)
712 #define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1)
713 #define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2)
714 #define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3)
715 #define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
716 #define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7)
728 #define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0)
729 #define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1)
730 #define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4)
731 #define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5)
732 #define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6)
736 #define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3)
740 #define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7)
745 #define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0)
746 #define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1)
747 #define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4)
748 #define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5)
749 #define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6)
761 #define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0)
762 #define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1)
763 #define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4)
764 #define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
765 #define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6)
769 #define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3)
773 #define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7)
778 #define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0)
779 #define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1)
780 #define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4)
781 #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
782 #define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6)
785 #define OP_GCSPUSHX sys_insn(1, 0, 7, 7, 4)
786 #define OP_GCSPOPCX sys_insn(1, 0, 7, 7, 5)
787 #define OP_GCSPOPX sys_insn(1, 0, 7, 7, 6)
788 #define OP_GCSPUSHM sys_insn(1, 3, 7, 7, 0)
790 #define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4)
791 #define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5)
792 #define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4)
793 #define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5)
794 #define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6)
795 #define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)
819 #define SCTLR_ELx_SA (BIT(3))
938 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
969 #define TRFCR_EL2_CX BIT(3)
979 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
984 #define ICH_LR_STATE (3ULL << 62)
995 #define ICH_HCR_NPIE (1 << 3)
1006 #define ICH_VMCR_FIQ_EN_SHIFT 3
1013 #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
1015 #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
1025 #define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT)
1027 #define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT)
1160 * set mask are set. Other bits are left as-is.