Lines Matching +full:0 +full:- +full:7

1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22  *	[20-19] : Op0
23  *	[18-16] : Op1
24  *	[15-12] : CRn
25  *	[11-8]  : CRm
26  *	[7-5]   : Op2
29 #define Op0_mask	0x3
31 #define Op1_mask	0x7
33 #define CRn_mask	0xf
35 #define CRm_mask	0xf
37 #define Op2_mask	0x7
67 #define __INSTR_BSWAP(x)		((((x) << 24) & 0xff000000)	| \
68 					 (((x) <<  8) & 0x00ff0000)	| \
69 					 (((x) >>  8) & 0x0000ff00)	| \
70 					 (((x) >> 24) & 0x000000ff))
83  * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
86  *	Op0 = 0, CRn = 4
89  *	Rt = 0x1f
93 #define SET_PSTATE(x, r)		__emit_inst(0xd500401f | PSTATE_ ## r | ((!!x) << PSTATE_Imm_shift))
95 #define PSTATE_PAN			pstate_field(0, 4)
96 #define PSTATE_UAO			pstate_field(0, 3)
113 	__emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
115 #define SB_BARRIER_INSN			__SYS_BARRIER_INSN(0, 7, 31)
117 #define SYS_DC_ISW			sys_insn(1, 0, 7, 6, 2)
118 #define SYS_DC_IGSW			sys_insn(1, 0, 7, 6, 4)
119 #define SYS_DC_IGDSW			sys_insn(1, 0, 7, 6, 6)
120 #define SYS_DC_CSW			sys_insn(1, 0, 7, 10, 2)
121 #define SYS_DC_CGSW			sys_insn(1, 0, 7, 10, 4)
122 #define SYS_DC_CGDSW			sys_insn(1, 0, 7, 10, 6)
123 #define SYS_DC_CISW			sys_insn(1, 0, 7, 14, 2)
124 #define SYS_DC_CIGSW			sys_insn(1, 0, 7, 14, 4)
125 #define SYS_DC_CIGDSW			sys_insn(1, 0, 7, 14, 6)
127 #define SYS_IC_IALLUIS			sys_insn(1, 0, 7, 1, 0)
128 #define SYS_IC_IALLU			sys_insn(1, 0, 7, 5, 0)
129 #define SYS_IC_IVAU			sys_insn(1, 3, 7, 5, 1)
131 #define SYS_DC_IVAC			sys_insn(1, 0, 7, 6, 1)
132 #define SYS_DC_IGVAC			sys_insn(1, 0, 7, 6, 3)
133 #define SYS_DC_IGDVAC			sys_insn(1, 0, 7, 6, 5)
135 #define SYS_DC_CVAC			sys_insn(1, 3, 7, 10, 1)
136 #define SYS_DC_CGVAC			sys_insn(1, 3, 7, 10, 3)
137 #define SYS_DC_CGDVAC			sys_insn(1, 3, 7, 10, 5)
139 #define SYS_DC_CVAU			sys_insn(1, 3, 7, 11, 1)
141 #define SYS_DC_CVAP			sys_insn(1, 3, 7, 12, 1)
142 #define SYS_DC_CGVAP			sys_insn(1, 3, 7, 12, 3)
143 #define SYS_DC_CGDVAP			sys_insn(1, 3, 7, 12, 5)
145 #define SYS_DC_CVADP			sys_insn(1, 3, 7, 13, 1)
146 #define SYS_DC_CGVADP			sys_insn(1, 3, 7, 13, 3)
147 #define SYS_DC_CGDVADP			sys_insn(1, 3, 7, 13, 5)
149 #define SYS_DC_CIVAC			sys_insn(1, 3, 7, 14, 1)
150 #define SYS_DC_CIGVAC			sys_insn(1, 3, 7, 14, 3)
151 #define SYS_DC_CIGDVAC			sys_insn(1, 3, 7, 14, 5)
154 #define SYS_DC_ZVA			sys_insn(1, 3, 7, 4, 1)
155 #define SYS_DC_GVA			sys_insn(1, 3, 7, 4, 3)
156 #define SYS_DC_GZVA			sys_insn(1, 3, 7, 4, 4)
164 #include "asm/sysreg-defs.h"
170 #define SYS_SVCR_SMSTOP_SM_EL0		sys_reg(0, 3, 4, 2, 3)
171 #define SYS_SVCR_SMSTART_SM_EL0		sys_reg(0, 3, 4, 3, 3)
172 #define SYS_SVCR_SMSTOP_SMZA_EL0	sys_reg(0, 3, 4, 6, 3)
174 #define SYS_DBGBVRn_EL1(n)		sys_reg(2, 0, 0, n, 4)
175 #define SYS_DBGBCRn_EL1(n)		sys_reg(2, 0, 0, n, 5)
176 #define SYS_DBGWVRn_EL1(n)		sys_reg(2, 0, 0, n, 6)
177 #define SYS_DBGWCRn_EL1(n)		sys_reg(2, 0, 0, n, 7)
178 #define SYS_MDRAR_EL1			sys_reg(2, 0, 1, 0, 0)
180 #define SYS_OSLSR_EL1			sys_reg(2, 0, 1, 1, 4)
181 #define OSLSR_EL1_OSLM_MASK		(BIT(3) | BIT(0))
182 #define OSLSR_EL1_OSLM_NI		0
186 #define SYS_OSDLR_EL1			sys_reg(2, 0, 1, 3, 4)
187 #define SYS_DBGPRCR_EL1			sys_reg(2, 0, 1, 4, 4)
188 #define SYS_DBGCLAIMSET_EL1		sys_reg(2, 0, 7, 8, 6)
189 #define SYS_DBGCLAIMCLR_EL1		sys_reg(2, 0, 7, 9, 6)
190 #define SYS_DBGAUTHSTATUS_EL1		sys_reg(2, 0, 7, 14, 6)
191 #define SYS_MDCCSR_EL0			sys_reg(2, 3, 0, 1, 0)
192 #define SYS_DBGDTR_EL0			sys_reg(2, 3, 0, 4, 0)
193 #define SYS_DBGDTRRX_EL0		sys_reg(2, 3, 0, 5, 0)
194 #define SYS_DBGDTRTX_EL0		sys_reg(2, 3, 0, 5, 0)
195 #define SYS_DBGVCR32_EL2		sys_reg(2, 4, 0, 7, 0)
197 #define SYS_BRBINF_EL1(n)		sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
198 #define SYS_BRBINFINJ_EL1		sys_reg(2, 1, 9, 1, 0)
203 #define SYS_BRBTS_EL1			sys_reg(2, 1, 9, 0, 2)
205 #define SYS_BRBCR_EL1			sys_reg(2, 1, 9, 0, 0)
206 #define SYS_BRBFCR_EL1			sys_reg(2, 1, 9, 0, 1)
207 #define SYS_BRBIDR0_EL1			sys_reg(2, 1, 9, 2, 0)
209 #define SYS_TRCITECR_EL1		sys_reg(3, 0, 1, 2, 3)
210 #define SYS_TRCACATR(m)			sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
211 #define SYS_TRCACVR(m)			sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))
212 #define SYS_TRCAUTHSTATUS		sys_reg(2, 1, 7, 14, 6)
213 #define SYS_TRCAUXCTLR			sys_reg(2, 1, 0, 6, 0)
214 #define SYS_TRCBBCTLR			sys_reg(2, 1, 0, 15, 0)
215 #define SYS_TRCCCCTLR			sys_reg(2, 1, 0, 14, 0)
216 #define SYS_TRCCIDCCTLR0		sys_reg(2, 1, 3, 0, 2)
218 #define SYS_TRCCIDCVR(m)		sys_reg(2, 1, 3, ((m & 7) << 1), 0)
219 #define SYS_TRCCLAIMCLR			sys_reg(2, 1, 7, 9, 6)
220 #define SYS_TRCCLAIMSET			sys_reg(2, 1, 7, 8, 6)
221 #define SYS_TRCCNTCTLR(m)		sys_reg(2, 1, 0, (4 | (m & 3)), 5)
222 #define SYS_TRCCNTRLDVR(m)		sys_reg(2, 1, 0, (0 | (m & 3)), 5)
223 #define SYS_TRCCNTVR(m)			sys_reg(2, 1, 0, (8 | (m & 3)), 5)
224 #define SYS_TRCCONFIGR			sys_reg(2, 1, 0, 4, 0)
225 #define SYS_TRCDEVARCH			sys_reg(2, 1, 7, 15, 6)
226 #define SYS_TRCDEVID			sys_reg(2, 1, 7, 2, 7)
227 #define SYS_TRCEVENTCTL0R		sys_reg(2, 1, 0, 8, 0)
228 #define SYS_TRCEVENTCTL1R		sys_reg(2, 1, 0, 9, 0)
229 #define SYS_TRCEXTINSELR(m)		sys_reg(2, 1, 0, (8 | (m & 3)), 4)
230 #define SYS_TRCIDR0			sys_reg(2, 1, 0, 8, 7)
231 #define SYS_TRCIDR10			sys_reg(2, 1, 0, 2, 6)
232 #define SYS_TRCIDR11			sys_reg(2, 1, 0, 3, 6)
233 #define SYS_TRCIDR12			sys_reg(2, 1, 0, 4, 6)
234 #define SYS_TRCIDR13			sys_reg(2, 1, 0, 5, 6)
235 #define SYS_TRCIDR1			sys_reg(2, 1, 0, 9, 7)
236 #define SYS_TRCIDR2			sys_reg(2, 1, 0, 10, 7)
237 #define SYS_TRCIDR3			sys_reg(2, 1, 0, 11, 7)
238 #define SYS_TRCIDR4			sys_reg(2, 1, 0, 12, 7)
239 #define SYS_TRCIDR5			sys_reg(2, 1, 0, 13, 7)
240 #define SYS_TRCIDR6			sys_reg(2, 1, 0, 14, 7)
241 #define SYS_TRCIDR7			sys_reg(2, 1, 0, 15, 7)
242 #define SYS_TRCIDR8			sys_reg(2, 1, 0, 0, 6)
243 #define SYS_TRCIDR9			sys_reg(2, 1, 0, 1, 6)
244 #define SYS_TRCIMSPEC(m)		sys_reg(2, 1, 0, (m & 7), 7)
245 #define SYS_TRCITEEDCR			sys_reg(2, 1, 0, 2, 1)
247 #define SYS_TRCPRGCTLR			sys_reg(2, 1, 0, 1, 0)
248 #define SYS_TRCQCTLR			sys_reg(2, 1, 0, 1, 1)
249 #define SYS_TRCRSCTLR(m)		sys_reg(2, 1, 1, (m & 15), (0 | (m >> 4)))
250 #define SYS_TRCRSR			sys_reg(2, 1, 0, 10, 0)
251 #define SYS_TRCSEQEVR(m)		sys_reg(2, 1, 0, (m & 3), 4)
252 #define SYS_TRCSEQRSTEVR		sys_reg(2, 1, 0, 6, 4)
253 #define SYS_TRCSEQSTR			sys_reg(2, 1, 0, 7, 4)
254 #define SYS_TRCSSCCR(m)			sys_reg(2, 1, 1, (m & 7), 2)
255 #define SYS_TRCSSCSR(m)			sys_reg(2, 1, 1, (8 | (m & 7)), 2)
256 #define SYS_TRCSSPCICR(m)		sys_reg(2, 1, 1, (m & 7), 3)
257 #define SYS_TRCSTALLCTLR		sys_reg(2, 1, 0, 11, 0)
258 #define SYS_TRCSTATR			sys_reg(2, 1, 0, 3, 0)
259 #define SYS_TRCSYNCPR			sys_reg(2, 1, 0, 13, 0)
260 #define SYS_TRCTRACEIDR			sys_reg(2, 1, 0, 0, 1)
261 #define SYS_TRCTSCTLR			sys_reg(2, 1, 0, 12, 0)
262 #define SYS_TRCVICTLR			sys_reg(2, 1, 0, 0, 2)
263 #define SYS_TRCVIIECTLR			sys_reg(2, 1, 0, 1, 2)
264 #define SYS_TRCVIPCSSCTLR		sys_reg(2, 1, 0, 3, 2)
265 #define SYS_TRCVISSCTLR			sys_reg(2, 1, 0, 2, 2)
268 #define SYS_TRCVMIDCVR(m)		sys_reg(2, 1, 3, ((m & 7) << 1), 1)
271 #define SYS_TRCOSLAR			sys_reg(2, 1, 1, 0, 4)
273 #define SYS_BRBCR_EL2			sys_reg(2, 4, 9, 0, 0)
275 #define SYS_MIDR_EL1			sys_reg(3, 0, 0, 0, 0)
276 #define SYS_MPIDR_EL1			sys_reg(3, 0, 0, 0, 5)
277 #define SYS_REVIDR_EL1			sys_reg(3, 0, 0, 0, 6)
279 #define SYS_ACTLR_EL1			sys_reg(3, 0, 1, 0, 1)
280 #define SYS_RGSR_EL1			sys_reg(3, 0, 1, 0, 5)
281 #define SYS_GCR_EL1			sys_reg(3, 0, 1, 0, 6)
283 #define SYS_TRFCR_EL1			sys_reg(3, 0, 1, 2, 1)
285 #define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)
287 #define SYS_APIAKEYLO_EL1		sys_reg(3, 0, 2, 1, 0)
288 #define SYS_APIAKEYHI_EL1		sys_reg(3, 0, 2, 1, 1)
289 #define SYS_APIBKEYLO_EL1		sys_reg(3, 0, 2, 1, 2)
290 #define SYS_APIBKEYHI_EL1		sys_reg(3, 0, 2, 1, 3)
292 #define SYS_APDAKEYLO_EL1		sys_reg(3, 0, 2, 2, 0)
293 #define SYS_APDAKEYHI_EL1		sys_reg(3, 0, 2, 2, 1)
294 #define SYS_APDBKEYLO_EL1		sys_reg(3, 0, 2, 2, 2)
295 #define SYS_APDBKEYHI_EL1		sys_reg(3, 0, 2, 2, 3)
297 #define SYS_APGAKEYLO_EL1		sys_reg(3, 0, 2, 3, 0)
298 #define SYS_APGAKEYHI_EL1		sys_reg(3, 0, 2, 3, 1)
300 #define SYS_SPSR_EL1			sys_reg(3, 0, 4, 0, 0)
301 #define SYS_ELR_EL1			sys_reg(3, 0, 4, 0, 1)
303 #define SYS_ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)
305 #define SYS_AFSR0_EL1			sys_reg(3, 0, 5, 1, 0)
306 #define SYS_AFSR1_EL1			sys_reg(3, 0, 5, 1, 1)
307 #define SYS_ESR_EL1			sys_reg(3, 0, 5, 2, 0)
309 #define SYS_ERRIDR_EL1			sys_reg(3, 0, 5, 3, 0)
310 #define SYS_ERRSELR_EL1			sys_reg(3, 0, 5, 3, 1)
311 #define SYS_ERXFR_EL1			sys_reg(3, 0, 5, 4, 0)
312 #define SYS_ERXCTLR_EL1			sys_reg(3, 0, 5, 4, 1)
313 #define SYS_ERXSTATUS_EL1		sys_reg(3, 0, 5, 4, 2)
314 #define SYS_ERXADDR_EL1			sys_reg(3, 0, 5, 4, 3)
315 #define SYS_ERXPFGF_EL1			sys_reg(3, 0, 5, 4, 4)
316 #define SYS_ERXPFGCTL_EL1		sys_reg(3, 0, 5, 4, 5)
317 #define SYS_ERXPFGCDN_EL1		sys_reg(3, 0, 5, 4, 6)
318 #define SYS_ERXMISC0_EL1		sys_reg(3, 0, 5, 5, 0)
319 #define SYS_ERXMISC1_EL1		sys_reg(3, 0, 5, 5, 1)
320 #define SYS_ERXMISC2_EL1		sys_reg(3, 0, 5, 5, 2)
321 #define SYS_ERXMISC3_EL1		sys_reg(3, 0, 5, 5, 3)
322 #define SYS_TFSR_EL1			sys_reg(3, 0, 5, 6, 0)
323 #define SYS_TFSRE0_EL1			sys_reg(3, 0, 5, 6, 1)
325 #define SYS_PAR_EL1			sys_reg(3, 0, 7, 4, 0)
327 #define SYS_PAR_EL1_F			BIT(0)
333 	 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
346 #define PMBSR_EL1_BUF_BSC_FULL		0x1UL
350 #define TRBSR_EL1_BSC_MASK		GENMASK(5, 0)
351 #define TRBSR_EL1_BSC_SHIFT		0
353 #define SYS_PMINTENSET_EL1		sys_reg(3, 0, 9, 14, 1)
354 #define SYS_PMINTENCLR_EL1		sys_reg(3, 0, 9, 14, 2)
356 #define SYS_PMMIR_EL1			sys_reg(3, 0, 9, 14, 6)
358 #define SYS_MAIR_EL1			sys_reg(3, 0, 10, 2, 0)
359 #define SYS_AMAIR_EL1			sys_reg(3, 0, 10, 3, 0)
361 #define SYS_VBAR_EL1			sys_reg(3, 0, 12, 0, 0)
362 #define SYS_DISR_EL1			sys_reg(3, 0, 12, 1, 1)
364 #define SYS_ICC_IAR0_EL1		sys_reg(3, 0, 12, 8, 0)
365 #define SYS_ICC_EOIR0_EL1		sys_reg(3, 0, 12, 8, 1)
366 #define SYS_ICC_HPPIR0_EL1		sys_reg(3, 0, 12, 8, 2)
367 #define SYS_ICC_BPR0_EL1		sys_reg(3, 0, 12, 8, 3)
368 #define SYS_ICC_AP0Rn_EL1(n)		sys_reg(3, 0, 12, 8, 4 | n)
369 #define SYS_ICC_AP0R0_EL1		SYS_ICC_AP0Rn_EL1(0)
373 #define SYS_ICC_AP1Rn_EL1(n)		sys_reg(3, 0, 12, 9, n)
374 #define SYS_ICC_AP1R0_EL1		SYS_ICC_AP1Rn_EL1(0)
378 #define SYS_ICC_DIR_EL1			sys_reg(3, 0, 12, 11, 1)
379 #define SYS_ICC_RPR_EL1			sys_reg(3, 0, 12, 11, 3)
380 #define SYS_ICC_SGI1R_EL1		sys_reg(3, 0, 12, 11, 5)
381 #define SYS_ICC_ASGI1R_EL1		sys_reg(3, 0, 12, 11, 6)
382 #define SYS_ICC_SGI0R_EL1		sys_reg(3, 0, 12, 11, 7)
383 #define SYS_ICC_IAR1_EL1		sys_reg(3, 0, 12, 12, 0)
384 #define SYS_ICC_EOIR1_EL1		sys_reg(3, 0, 12, 12, 1)
385 #define SYS_ICC_HPPIR1_EL1		sys_reg(3, 0, 12, 12, 2)
386 #define SYS_ICC_BPR1_EL1		sys_reg(3, 0, 12, 12, 3)
387 #define SYS_ICC_CTLR_EL1		sys_reg(3, 0, 12, 12, 4)
388 #define SYS_ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)
389 #define SYS_ICC_IGRPEN0_EL1		sys_reg(3, 0, 12, 12, 6)
390 #define SYS_ICC_IGRPEN1_EL1		sys_reg(3, 0, 12, 12, 7)
392 #define SYS_ACCDATA_EL1			sys_reg(3, 0, 13, 0, 5)
394 #define SYS_CNTKCTL_EL1			sys_reg(3, 0, 14, 1, 0)
396 #define SYS_AIDR_EL1			sys_reg(3, 1, 0, 0, 7)
398 #define SYS_RNDR_EL0			sys_reg(3, 3, 2, 4, 0)
401 #define SYS_PMCR_EL0			sys_reg(3, 3, 9, 12, 0)
408 #define SYS_PMCEID1_EL0			sys_reg(3, 3, 9, 12, 7)
409 #define SYS_PMCCNTR_EL0			sys_reg(3, 3, 9, 13, 0)
412 #define SYS_PMUSERENR_EL0		sys_reg(3, 3, 9, 14, 0)
415 #define SYS_TPIDR_EL0			sys_reg(3, 3, 13, 0, 2)
416 #define SYS_TPIDRRO_EL0			sys_reg(3, 3, 13, 0, 3)
417 #define SYS_TPIDR2_EL0			sys_reg(3, 3, 13, 0, 5)
419 #define SYS_SCXTNUM_EL0			sys_reg(3, 3, 13, 0, 7)
423 #define SYS_AMCR_EL0			SYS_AM_EL0(2, 0)
429 #define SYS_AMCNTENCLR1_EL0		SYS_AM_EL0(3, 0)
433  * Group 0 of activity monitors (architected):
435  * Counter:       11   011  1101  010:n<3>  n<2:0>
436  * Type:          11   011  1101  011:n<3>  n<2:0>
437  * n: 0-15
441  * Counter:       11   011  1101  110:n<3>  n<2:0>
442  * Type:          11   011  1101  111:n<3>  n<2:0>
443  * n: 0-15
446 #define SYS_AMEVCNTR0_EL0(n)		SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
447 #define SYS_AMEVTYPER0_EL0(n)		SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
448 #define SYS_AMEVCNTR1_EL0(n)		SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
449 #define SYS_AMEVTYPER1_EL0(n)		SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
452 #define SYS_AMEVCNTR0_CORE_EL0		SYS_AMEVCNTR0_EL0(0)
457 #define SYS_CNTFRQ_EL0			sys_reg(3, 3, 14, 0, 0)
459 #define SYS_CNTPCT_EL0			sys_reg(3, 3, 14, 0, 1)
460 #define SYS_CNTPCTSS_EL0		sys_reg(3, 3, 14, 0, 5)
461 #define SYS_CNTVCTSS_EL0		sys_reg(3, 3, 14, 0, 6)
463 #define SYS_CNTP_TVAL_EL0		sys_reg(3, 3, 14, 2, 0)
470 #define SYS_AARCH32_CNTP_TVAL		sys_reg(0, 0, 14, 2, 0)
471 #define SYS_AARCH32_CNTP_CTL		sys_reg(0, 0, 14, 2, 1)
472 #define SYS_AARCH32_CNTPCT		sys_reg(0, 0, 0, 14, 0)
473 #define SYS_AARCH32_CNTP_CVAL		sys_reg(0, 2, 0, 14, 0)
474 #define SYS_AARCH32_CNTPCTSS		sys_reg(0, 8, 0, 14, 0)
476 #define __PMEV_op2(n)			((n) & 0x7)
477 #define __CNTR_CRm(n)			(0x8 | (((n) >> 3) & 0x3))
479 #define __TYPER_CRm(n)			(0xc | (((n) >> 3) & 0x3))
482 #define SYS_PMCCFILTR_EL0		sys_reg(3, 3, 14, 15, 7)
484 #define SYS_VPIDR_EL2			sys_reg(3, 4, 0, 0, 0)
485 #define SYS_VMPIDR_EL2			sys_reg(3, 4, 0, 0, 5)
487 #define SYS_SCTLR_EL2			sys_reg(3, 4, 1, 0, 0)
488 #define SYS_ACTLR_EL2			sys_reg(3, 4, 1, 0, 1)
489 #define SYS_SCTLR2_EL2			sys_reg(3, 4, 1, 0, 3)
490 #define SYS_HCR_EL2			sys_reg(3, 4, 1, 1, 0)
494 #define SYS_HACR_EL2			sys_reg(3, 4, 1, 1, 7)
496 #define SYS_TTBR0_EL2			sys_reg(3, 4, 2, 0, 0)
497 #define SYS_TTBR1_EL2			sys_reg(3, 4, 2, 0, 1)
498 #define SYS_TCR_EL2			sys_reg(3, 4, 2, 0, 2)
499 #define SYS_VTTBR_EL2			sys_reg(3, 4, 2, 1, 0)
503 #define SYS_VNCR_EL2			sys_reg(3, 4, 2, 2, 0)
505 #define SYS_SPSR_EL2			sys_reg(3, 4, 4, 0, 0)
506 #define SYS_ELR_EL2			sys_reg(3, 4, 4, 0, 1)
507 #define SYS_SP_EL1			sys_reg(3, 4, 4, 1, 0)
508 #define SYS_SPSR_irq			sys_reg(3, 4, 4, 3, 0)
512 #define SYS_IFSR32_EL2			sys_reg(3, 4, 5, 0, 1)
513 #define SYS_AFSR0_EL2			sys_reg(3, 4, 5, 1, 0)
515 #define SYS_ESR_EL2			sys_reg(3, 4, 5, 2, 0)
517 #define SYS_FPEXC32_EL2			sys_reg(3, 4, 5, 3, 0)
518 #define SYS_TFSR_EL2			sys_reg(3, 4, 5, 6, 0)
520 #define SYS_FAR_EL2			sys_reg(3, 4, 6, 0, 0)
521 #define SYS_HPFAR_EL2			sys_reg(3, 4, 6, 0, 4)
523 #define SYS_MAIR_EL2			sys_reg(3, 4, 10, 2, 0)
524 #define SYS_AMAIR_EL2			sys_reg(3, 4, 10, 3, 0)
525 #define SYS_MPAMHCR_EL2			sys_reg(3, 4, 10, 4, 0)
527 #define SYS_MPAM2_EL2			sys_reg(3, 4, 10, 5, 0)
529 #define SYS_MPAMVPM0_EL2		__SYS__MPAMVPMx_EL2(0)
536 #define SYS_MPAMVPM7_EL2		__SYS__MPAMVPMx_EL2(7)
538 #define SYS_VBAR_EL2			sys_reg(3, 4, 12, 0, 0)
539 #define SYS_RVBAR_EL2			sys_reg(3, 4, 12, 0, 1)
540 #define SYS_RMR_EL2			sys_reg(3, 4, 12, 0, 2)
543 #define SYS_ICH_AP0R0_EL2		__SYS__AP0Rx_EL2(0)
549 #define SYS_ICH_AP1R0_EL2		__SYS__AP1Rx_EL2(0)
556 #define SYS_ICH_HCR_EL2			sys_reg(3, 4, 12, 11, 0)
561 #define SYS_ICH_VMCR_EL2		sys_reg(3, 4, 12, 11, 7)
564 #define SYS_ICH_LR0_EL2			__SYS__LR0_EL2(0)
571 #define SYS_ICH_LR7_EL2			__SYS__LR0_EL2(7)
574 #define SYS_ICH_LR8_EL2			__SYS__LR8_EL2(0)
581 #define SYS_ICH_LR15_EL2		__SYS__LR8_EL2(7)
583 #define SYS_CONTEXTIDR_EL2		sys_reg(3, 4, 13, 0, 1)
584 #define SYS_TPIDR_EL2			sys_reg(3, 4, 13, 0, 2)
585 #define SYS_SCXTNUM_EL2			sys_reg(3, 4, 13, 0, 7)
587 #define __AMEV_op2(m)			(m & 0x7)
588 #define __AMEV_CRm(n, m)		(n | ((m & 0x8) >> 3))
589 #define __SYS__AMEVCNTVOFF0n_EL2(m)	sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m))
591 #define __SYS__AMEVCNTVOFF1n_EL2(m)	sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m))
594 #define SYS_CNTVOFF_EL2			sys_reg(3, 4, 14, 0, 3)
595 #define SYS_CNTHCTL_EL2			sys_reg(3, 4, 14, 1, 0)
596 #define SYS_CNTHP_TVAL_EL2		sys_reg(3, 4, 14, 2, 0)
599 #define SYS_CNTHV_TVAL_EL2		sys_reg(3, 4, 14, 3, 0)
604 #define SYS_BRBCR_EL12			sys_reg(2, 5, 9, 0, 0)
605 #define SYS_SCTLR_EL12			sys_reg(3, 5, 1, 0, 0)
606 #define SYS_CPACR_EL12			sys_reg(3, 5, 1, 0, 2)
607 #define SYS_SCTLR2_EL12			sys_reg(3, 5, 1, 0, 3)
608 #define SYS_ZCR_EL12			sys_reg(3, 5, 1, 2, 0)
611 #define SYS_TTBR0_EL12			sys_reg(3, 5, 2, 0, 0)
612 #define SYS_TTBR1_EL12			sys_reg(3, 5, 2, 0, 1)
613 #define SYS_TCR_EL12			sys_reg(3, 5, 2, 0, 2)
614 #define SYS_TCR2_EL12			sys_reg(3, 5, 2, 0, 3)
615 #define SYS_SPSR_EL12			sys_reg(3, 5, 4, 0, 0)
616 #define SYS_ELR_EL12			sys_reg(3, 5, 4, 0, 1)
617 #define SYS_AFSR0_EL12			sys_reg(3, 5, 5, 1, 0)
619 #define SYS_ESR_EL12			sys_reg(3, 5, 5, 2, 0)
620 #define SYS_TFSR_EL12			sys_reg(3, 5, 5, 6, 0)
621 #define SYS_FAR_EL12			sys_reg(3, 5, 6, 0, 0)
622 #define SYS_PMSCR_EL12			sys_reg(3, 5, 9, 9, 0)
623 #define SYS_MAIR_EL12			sys_reg(3, 5, 10, 2, 0)
624 #define SYS_AMAIR_EL12			sys_reg(3, 5, 10, 3, 0)
625 #define SYS_VBAR_EL12			sys_reg(3, 5, 12, 0, 0)
626 #define SYS_CONTEXTIDR_EL12		sys_reg(3, 5, 13, 0, 1)
627 #define SYS_SCXTNUM_EL12		sys_reg(3, 5, 13, 0, 7)
628 #define SYS_CNTKCTL_EL12		sys_reg(3, 5, 14, 1, 0)
629 #define SYS_CNTP_TVAL_EL02		sys_reg(3, 5, 14, 2, 0)
632 #define SYS_CNTV_TVAL_EL02		sys_reg(3, 5, 14, 3, 0)
636 #define SYS_SP_EL2			sys_reg(3, 6,  4, 1, 0)
640 #define AT_CRn 7
642 #define OP_AT_S1E1R	sys_insn(AT_Op0, 0, AT_CRn, 8, 0)
643 #define OP_AT_S1E1W	sys_insn(AT_Op0, 0, AT_CRn, 8, 1)
644 #define OP_AT_S1E0R	sys_insn(AT_Op0, 0, AT_CRn, 8, 2)
645 #define OP_AT_S1E0W	sys_insn(AT_Op0, 0, AT_CRn, 8, 3)
646 #define OP_AT_S1E1RP	sys_insn(AT_Op0, 0, AT_CRn, 9, 0)
647 #define OP_AT_S1E1WP	sys_insn(AT_Op0, 0, AT_CRn, 9, 1)
648 #define OP_AT_S1E1A	sys_insn(AT_Op0, 0, AT_CRn, 9, 2)
649 #define OP_AT_S1E2R	sys_insn(AT_Op0, 4, AT_CRn, 8, 0)
654 #define OP_AT_S12E0W	sys_insn(AT_Op0, 4, AT_CRn, 8, 7)
657 #define OP_TLBI_VMALLE1OS		sys_insn(1, 0, 8, 1, 0)
658 #define OP_TLBI_VAE1OS			sys_insn(1, 0, 8, 1, 1)
659 #define OP_TLBI_ASIDE1OS		sys_insn(1, 0, 8, 1, 2)
660 #define OP_TLBI_VAAE1OS			sys_insn(1, 0, 8, 1, 3)
661 #define OP_TLBI_VALE1OS			sys_insn(1, 0, 8, 1, 5)
662 #define OP_TLBI_VAALE1OS		sys_insn(1, 0, 8, 1, 7)
663 #define OP_TLBI_RVAE1IS			sys_insn(1, 0, 8, 2, 1)
664 #define OP_TLBI_RVAAE1IS		sys_insn(1, 0, 8, 2, 3)
665 #define OP_TLBI_RVALE1IS		sys_insn(1, 0, 8, 2, 5)
666 #define OP_TLBI_RVAALE1IS		sys_insn(1, 0, 8, 2, 7)
667 #define OP_TLBI_VMALLE1IS		sys_insn(1, 0, 8, 3, 0)
668 #define OP_TLBI_VAE1IS			sys_insn(1, 0, 8, 3, 1)
669 #define OP_TLBI_ASIDE1IS		sys_insn(1, 0, 8, 3, 2)
670 #define OP_TLBI_VAAE1IS			sys_insn(1, 0, 8, 3, 3)
671 #define OP_TLBI_VALE1IS			sys_insn(1, 0, 8, 3, 5)
672 #define OP_TLBI_VAALE1IS		sys_insn(1, 0, 8, 3, 7)
673 #define OP_TLBI_RVAE1OS			sys_insn(1, 0, 8, 5, 1)
674 #define OP_TLBI_RVAAE1OS		sys_insn(1, 0, 8, 5, 3)
675 #define OP_TLBI_RVALE1OS		sys_insn(1, 0, 8, 5, 5)
676 #define OP_TLBI_RVAALE1OS		sys_insn(1, 0, 8, 5, 7)
677 #define OP_TLBI_RVAE1			sys_insn(1, 0, 8, 6, 1)
678 #define OP_TLBI_RVAAE1			sys_insn(1, 0, 8, 6, 3)
679 #define OP_TLBI_RVALE1			sys_insn(1, 0, 8, 6, 5)
680 #define OP_TLBI_RVAALE1			sys_insn(1, 0, 8, 6, 7)
681 #define OP_TLBI_VMALLE1			sys_insn(1, 0, 8, 7, 0)
682 #define OP_TLBI_VAE1			sys_insn(1, 0, 8, 7, 1)
683 #define OP_TLBI_ASIDE1			sys_insn(1, 0, 8, 7, 2)
684 #define OP_TLBI_VAAE1			sys_insn(1, 0, 8, 7, 3)
685 #define OP_TLBI_VALE1			sys_insn(1, 0, 8, 7, 5)
686 #define OP_TLBI_VAALE1			sys_insn(1, 0, 8, 7, 7)
687 #define OP_TLBI_VMALLE1OSNXS		sys_insn(1, 0, 9, 1, 0)
688 #define OP_TLBI_VAE1OSNXS		sys_insn(1, 0, 9, 1, 1)
689 #define OP_TLBI_ASIDE1OSNXS		sys_insn(1, 0, 9, 1, 2)
690 #define OP_TLBI_VAAE1OSNXS		sys_insn(1, 0, 9, 1, 3)
691 #define OP_TLBI_VALE1OSNXS		sys_insn(1, 0, 9, 1, 5)
692 #define OP_TLBI_VAALE1OSNXS		sys_insn(1, 0, 9, 1, 7)
693 #define OP_TLBI_RVAE1ISNXS		sys_insn(1, 0, 9, 2, 1)
694 #define OP_TLBI_RVAAE1ISNXS		sys_insn(1, 0, 9, 2, 3)
695 #define OP_TLBI_RVALE1ISNXS		sys_insn(1, 0, 9, 2, 5)
696 #define OP_TLBI_RVAALE1ISNXS		sys_insn(1, 0, 9, 2, 7)
697 #define OP_TLBI_VMALLE1ISNXS		sys_insn(1, 0, 9, 3, 0)
698 #define OP_TLBI_VAE1ISNXS		sys_insn(1, 0, 9, 3, 1)
699 #define OP_TLBI_ASIDE1ISNXS		sys_insn(1, 0, 9, 3, 2)
700 #define OP_TLBI_VAAE1ISNXS		sys_insn(1, 0, 9, 3, 3)
701 #define OP_TLBI_VALE1ISNXS		sys_insn(1, 0, 9, 3, 5)
702 #define OP_TLBI_VAALE1ISNXS		sys_insn(1, 0, 9, 3, 7)
703 #define OP_TLBI_RVAE1OSNXS		sys_insn(1, 0, 9, 5, 1)
704 #define OP_TLBI_RVAAE1OSNXS		sys_insn(1, 0, 9, 5, 3)
705 #define OP_TLBI_RVALE1OSNXS		sys_insn(1, 0, 9, 5, 5)
706 #define OP_TLBI_RVAALE1OSNXS		sys_insn(1, 0, 9, 5, 7)
707 #define OP_TLBI_RVAE1NXS		sys_insn(1, 0, 9, 6, 1)
708 #define OP_TLBI_RVAAE1NXS		sys_insn(1, 0, 9, 6, 3)
709 #define OP_TLBI_RVALE1NXS		sys_insn(1, 0, 9, 6, 5)
710 #define OP_TLBI_RVAALE1NXS		sys_insn(1, 0, 9, 6, 7)
711 #define OP_TLBI_VMALLE1NXS		sys_insn(1, 0, 9, 7, 0)
712 #define OP_TLBI_VAE1NXS			sys_insn(1, 0, 9, 7, 1)
713 #define OP_TLBI_ASIDE1NXS		sys_insn(1, 0, 9, 7, 2)
714 #define OP_TLBI_VAAE1NXS		sys_insn(1, 0, 9, 7, 3)
715 #define OP_TLBI_VALE1NXS		sys_insn(1, 0, 9, 7, 5)
716 #define OP_TLBI_VAALE1NXS		sys_insn(1, 0, 9, 7, 7)
717 #define OP_TLBI_IPAS2E1IS		sys_insn(1, 4, 8, 0, 1)
718 #define OP_TLBI_RIPAS2E1IS		sys_insn(1, 4, 8, 0, 2)
719 #define OP_TLBI_IPAS2LE1IS		sys_insn(1, 4, 8, 0, 5)
720 #define OP_TLBI_RIPAS2LE1IS		sys_insn(1, 4, 8, 0, 6)
721 #define OP_TLBI_ALLE2OS			sys_insn(1, 4, 8, 1, 0)
728 #define OP_TLBI_ALLE2IS			sys_insn(1, 4, 8, 3, 0)
733 #define OP_TLBI_IPAS2E1OS		sys_insn(1, 4, 8, 4, 0)
740 #define OP_TLBI_RIPAS2LE1OS		sys_insn(1, 4, 8, 4, 7)
745 #define OP_TLBI_ALLE2			sys_insn(1, 4, 8, 7, 0)
746 #define OP_TLBI_VAE2			sys_insn(1, 4, 8, 7, 1)
747 #define OP_TLBI_ALLE1			sys_insn(1, 4, 8, 7, 4)
748 #define OP_TLBI_VALE2			sys_insn(1, 4, 8, 7, 5)
749 #define OP_TLBI_VMALLS12E1		sys_insn(1, 4, 8, 7, 6)
750 #define OP_TLBI_IPAS2E1ISNXS		sys_insn(1, 4, 9, 0, 1)
751 #define OP_TLBI_RIPAS2E1ISNXS		sys_insn(1, 4, 9, 0, 2)
752 #define OP_TLBI_IPAS2LE1ISNXS		sys_insn(1, 4, 9, 0, 5)
753 #define OP_TLBI_RIPAS2LE1ISNXS		sys_insn(1, 4, 9, 0, 6)
754 #define OP_TLBI_ALLE2OSNXS		sys_insn(1, 4, 9, 1, 0)
761 #define OP_TLBI_ALLE2ISNXS		sys_insn(1, 4, 9, 3, 0)
766 #define OP_TLBI_IPAS2E1OSNXS		sys_insn(1, 4, 9, 4, 0)
773 #define OP_TLBI_RIPAS2LE1OSNXS		sys_insn(1, 4, 9, 4, 7)
778 #define OP_TLBI_ALLE2NXS		sys_insn(1, 4, 9, 7, 0)
779 #define OP_TLBI_VAE2NXS			sys_insn(1, 4, 9, 7, 1)
780 #define OP_TLBI_ALLE1NXS		sys_insn(1, 4, 9, 7, 4)
781 #define OP_TLBI_VALE2NXS		sys_insn(1, 4, 9, 7, 5)
782 #define OP_TLBI_VMALLS12E1NXS		sys_insn(1, 4, 9, 7, 6)
785 #define OP_GCSPUSHX			sys_insn(1, 0, 7, 7, 4)
786 #define OP_GCSPOPCX			sys_insn(1, 0, 7, 7, 5)
787 #define OP_GCSPOPX			sys_insn(1, 0, 7, 7, 6)
788 #define OP_GCSPUSHM			sys_insn(1, 3, 7, 7, 0)
790 #define OP_BRB_IALL			sys_insn(1, 1, 7, 2, 4)
791 #define OP_BRB_INJ			sys_insn(1, 1, 7, 2, 5)
792 #define OP_CFP_RCTX			sys_insn(1, 3, 7, 3, 4)
793 #define OP_DVP_RCTX			sys_insn(1, 3, 7, 3, 5)
794 #define OP_COSP_RCTX			sys_insn(1, 3, 7, 3, 6)
795 #define OP_CPP_RCTX			sys_insn(1, 3, 7, 3, 7)
822 #define SCTLR_ELx_M	 (BIT(0))
833 #define ENDIAN_SET_EL2		0
848 #define ENDIAN_SET_EL1		0
865 #define MAIR_ATTR_DEVICE_nGnRnE		UL(0x00)
866 #define MAIR_ATTR_DEVICE_nGnRE		UL(0x04)
867 #define MAIR_ATTR_NORMAL_NC		UL(0x44)
868 #define MAIR_ATTR_NORMAL_TAGGED		UL(0xf0)
869 #define MAIR_ATTR_NORMAL		UL(0xff)
870 #define MAIR_ATTR_MASK			UL(0xff)
876 #define ID_AA64PFR0_EL1_ELx_64BIT_ONLY		0x1
877 #define ID_AA64PFR0_EL1_ELx_32BIT_64BIT		0x2
880 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN	0x0
882 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX	0x7
883 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN	0x0
884 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX	0x7
885 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN	0x1
887 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX	0xf
891 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT	0x0
892 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE		0x1
893 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN		0x2
894 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2		0x3
895 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX		0x7
933 #define SYS_GCR_EL1_EXCL_MASK	0xffffUL
938  * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
940 #define __MTE_TAG_MIN		(KASAN_TAG_MIN & 0xf)
941 #define __MTE_TAG_MAX		(KASAN_TAG_MAX & 0xf)
951 #define SYS_RGSR_EL1_TAG_MASK	0xfUL
953 #define SYS_RGSR_EL1_SEED_MASK	0xffffUL
956 #define SYS_TFSR_EL1_TF0_SHIFT	0
961 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
965 #define TRFCR_ELx_TS_MASK		((0x3UL) << TRFCR_ELx_TS_SHIFT)
966 #define TRFCR_ELx_TS_VIRTUAL		((0x1UL) << TRFCR_ELx_TS_SHIFT)
967 #define TRFCR_ELx_TS_GUEST_PHYSICAL	((0x2UL) << TRFCR_ELx_TS_SHIFT)
968 #define TRFCR_ELx_TS_PHYSICAL		((0x3UL) << TRFCR_ELx_TS_SHIFT)
971 #define TRFCR_ELx_E0TRE			BIT(0)
975 #define ICH_MISR_EOI		(1 << 0)
979 #define ICH_LR_VIRTUAL_ID_MASK	((1ULL << 32) - 1)
988 #define ICH_LR_PHYS_ID_MASK	(0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
990 #define ICH_LR_PRIORITY_MASK	(0xffULL << ICH_LR_PRIORITY_SHIFT)
993 #define ICH_HCR_EN		(1 << 0)
1001 #define ICH_HCR_EOIcount_MASK	(0x1f << ICH_HCR_EOIcount_SHIFT)
1013 #define ICH_VMCR_BPR1_MASK	(7 << ICH_VMCR_BPR1_SHIFT)
1015 #define ICH_VMCR_BPR0_MASK	(7 << ICH_VMCR_BPR0_SHIFT)
1017 #define ICH_VMCR_PMR_MASK	(0xffUL << ICH_VMCR_PMR_SHIFT)
1018 #define ICH_VMCR_ENG0_SHIFT	0
1025 #define ICH_VTR_PRI_BITS_MASK	(7 << ICH_VTR_PRI_BITS_SHIFT)
1027 #define ICH_VTR_ID_BITS_MASK	(7 << ICH_VTR_ID_BITS_SHIFT)
1039 #define PIE_NONE_O	0x0
1040 #define PIE_R_O		0x1
1041 #define PIE_X_O		0x2
1042 #define PIE_RX_O	0x3
1043 #define PIE_RW_O	0x5
1044 #define PIE_RWnX_O	0x6
1045 #define PIE_RWX_O	0x7
1046 #define PIE_R		0x8
1047 #define PIE_GCS		0x9
1048 #define PIE_RX		0xa
1049 #define PIE_RW		0xc
1050 #define PIE_RWX		0xe
1057 #define POE_NONE	UL(0x0)
1058 #define POE_R		UL(0x1)
1059 #define POE_X		UL(0x2)
1060 #define POE_RX		UL(0x3)
1061 #define POE_W		UL(0x4)
1062 #define POE_RW		UL(0x5)
1063 #define POE_XW		UL(0x6)
1064 #define POE_RXW		UL(0x7)
1065 #define POE_MASK	UL(0xf)
1075 	 __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt))
1079 	__emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt))
1092 	__emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt))	\
1098 	__emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt))	\
1123 	asm volatile("mrs %0, " __stringify(r) : "=r" (__val));	\
1135 } while (0)
1148 	asm volatile(__mrs_s("%0", r) : "=r" (__val));			\
1156 } while (0)
1160  * set mask are set. Other bits are left as-is.
1167 } while (0)
1174 } while (0)