Lines Matching +full:1 +full:v8
67 // x1 = shuffle32(x1, MASK(0, 3, 2, 1))
69 // x2 = shuffle32(x2, MASK(1, 0, 3, 2))
71 // x3 = shuffle32(x3, MASK(2, 1, 0, 3))
96 // x1 = shuffle32(x1, MASK(2, 1, 0, 3))
98 // x2 = shuffle32(x2, MASK(1, 0, 3, 2))
100 // x3 = shuffle32(x3, MASK(0, 3, 2, 1))
111 // x1: 1 data block output, o
112 // x2: 1 data block input, i
120 ld1 {v8.4s-v11.4s}, [x0]
127 add v0.4s, v0.4s, v8.4s
217 ld4r { v8.4s-v11.4s}, [x8], #16
228 mov a8, v8.s[0]
237 // x12 += counter values 1-4
276 add v8.4s, v8.4s, v12.4s
285 eor v16.16b, v4.16b, v8.16b
343 add v8.4s, v8.4s, v12.4s
352 eor v16.16b, v4.16b, v8.16b
414 add v8.4s, v8.4s, v13.4s
423 eor v18.16b, v7.16b, v8.16b
481 add v8.4s, v8.4s, v13.4s
490 eor v18.16b, v7.16b, v8.16b
519 // x1[0-3] += s0[1]
543 // x5[0-3] += s1[1]
564 // x9[0-3] += s2[1]
567 add v8.4s, v8.4s, v24.4s
585 // x13[0-3] += s3[1]
605 // interleave 32-bit words in state n, n+1
627 zip1 v24.4s, v8.4s, v9.4s
630 zip2 v25.4s, v8.4s, v9.4s
657 zip1 v8.2d, v17.2d, v19.2d
713 eor v24.16b, v24.16b, v8.16b
733 .Lt192: cbz x5, 1f // exactly 128 bytes?
746 1: st1 {v16.16b-v19.16b}, [x1]
764 tbl v0.16b, {v8.16b-v11.16b}, v4.16b
765 tbl v1.16b, {v8.16b-v11.16b}, v5.16b
766 tbl v2.16b, {v8.16b-v11.16b}, v6.16b
767 tbl v3.16b, {v8.16b-v11.16b}, v7.16b
801 .set .Li, .Li + 1
804 CTRINC: .word 1, 2, 3, 4