Lines Matching +full:shared +full:- +full:dma +full:- +full:pool
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include "k3-j784s4.dtsi"
16 compatible = "ti,am69-sk", "ti,j784s4";
20 stdout-path = "serial2:115200n8";
41 reserved_memory: reserved-memory {
42 #address-cells = <2>;
43 #size-cells = <2>;
48 no-map;
51 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
52 compatible = "shared-dma-pool";
54 no-map;
57 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
58 compatible = "shared-dma-pool";
60 no-map;
63 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
64 compatible = "shared-dma-pool";
66 no-map;
69 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
70 compatible = "shared-dma-pool";
72 no-map;
75 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
76 compatible = "shared-dma-pool";
78 no-map;
81 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
82 compatible = "shared-dma-pool";
84 no-map;
87 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
88 compatible = "shared-dma-pool";
90 no-map;
93 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
94 compatible = "shared-dma-pool";
96 no-map;
99 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
100 compatible = "shared-dma-pool";
102 no-map;
105 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
106 compatible = "shared-dma-pool";
108 no-map;
111 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
112 compatible = "shared-dma-pool";
114 no-map;
117 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
118 compatible = "shared-dma-pool";
120 no-map;
123 main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 {
124 compatible = "shared-dma-pool";
126 no-map;
129 main_r5fss2_core0_memory_region: r5f-memory@a6100000 {
130 compatible = "shared-dma-pool";
132 no-map;
135 main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 {
136 compatible = "shared-dma-pool";
138 no-map;
141 main_r5fss2_core1_memory_region: r5f-memory@a7100000 {
142 compatible = "shared-dma-pool";
144 no-map;
147 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
148 compatible = "shared-dma-pool";
150 no-map;
153 c71_0_memory_region: c71-memory@a8100000 {
154 compatible = "shared-dma-pool";
156 no-map;
159 c71_1_dma_memory_region: c71-dma-memory@a9000000 {
160 compatible = "shared-dma-pool";
162 no-map;
165 c71_1_memory_region: c71-memory@a9100000 {
166 compatible = "shared-dma-pool";
168 no-map;
171 c71_2_dma_memory_region: c71-dma-memory@aa000000 {
172 compatible = "shared-dma-pool";
174 no-map;
177 c71_2_memory_region: c71-memory@aa100000 {
178 compatible = "shared-dma-pool";
180 no-map;
183 c71_3_dma_memory_region: c71-dma-memory@ab000000 {
184 compatible = "shared-dma-pool";
186 no-map;
189 c71_3_memory_region: c71-memory@ab100000 {
190 compatible = "shared-dma-pool";
192 no-map;
196 vusb_main: regulator-vusb-main5v0 {
198 compatible = "regulator-fixed";
199 regulator-name = "vusb-main5v0";
200 regulator-min-microvolt = <5000000>;
201 regulator-max-microvolt = <5000000>;
202 regulator-always-on;
203 regulator-boot-on;
206 vsys_5v0: regulator-vsys5v0 {
208 compatible = "regulator-fixed";
209 regulator-name = "vsys_5v0";
210 regulator-min-microvolt = <5000000>;
211 regulator-max-microvolt = <5000000>;
212 vin-supply = <&vusb_main>;
213 regulator-always-on;
214 regulator-boot-on;
217 vsys_3v3: regulator-vsys3v3 {
219 compatible = "regulator-fixed";
220 regulator-name = "vsys_3v3";
221 regulator-min-microvolt = <3300000>;
222 regulator-max-microvolt = <3300000>;
223 vin-supply = <&vusb_main>;
224 regulator-always-on;
225 regulator-boot-on;
228 vdd_mmc1: regulator-sd {
230 compatible = "regulator-fixed";
231 regulator-name = "vdd_mmc1";
232 regulator-min-microvolt = <3300000>;
233 regulator-max-microvolt = <3300000>;
234 regulator-boot-on;
235 enable-active-high;
236 vin-supply = <&vsys_3v3>;
240 vdd_sd_dv: regulator-tlv71033 {
242 compatible = "regulator-gpio";
243 regulator-name = "tlv71033";
244 pinctrl-names = "default";
245 pinctrl-0 = <&vdd_sd_dv_pins_default>;
246 regulator-min-microvolt = <1800000>;
247 regulator-max-microvolt = <3300000>;
248 regulator-boot-on;
249 vin-supply = <&vsys_5v0>;
255 dp0_pwr_3v3: regulator-dp0-pwr {
256 compatible = "regulator-fixed";
257 regulator-name = "dp0-pwr";
258 regulator-min-microvolt = <3300000>;
259 regulator-max-microvolt = <3300000>;
260 pinctrl-names = "default";
261 pinctrl-0 = <&dp_pwr_en_pins_default>;
263 enable-active-high;
266 dp0: connector-dp0 {
267 compatible = "dp-connector";
269 type = "full-size";
270 dp-pwr-supply = <&dp0_pwr_3v3>;
274 remote-endpoint = <&dp0_out>;
279 connector-hdmi {
280 compatible = "hdmi-connector";
283 pinctrl-names = "default";
284 pinctrl-0 = <&hdmi_hpd_pins_default>;
285 ddc-i2c-bus = <&mcu_i2c1>;
286 hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; /* HDMI_HPD */
290 remote-endpoint = <&tfp410_out>;
295 bridge-dvi {
297 pinctrl-names = "default";
298 pinctrl-0 = <&hdmi_pdn_pins_default>;
299 powerdown-gpios = <&wkup_gpio0 14 GPIO_ACTIVE_LOW>; /* HDMI_PDn */
303 #address-cells = <1>;
304 #size-cells = <0>;
310 remote-endpoint = <&dpi1_out0>;
311 pclk-sample = <1>;
319 remote-endpoint = <&hdmi_connector_in>;
327 bootph-all;
328 main_uart8_pins_default: main-uart8-default-pins {
329 bootph-all;
330 pinctrl-single,pins = <
336 main_i2c0_pins_default: main-i2c0-default-pins {
337 pinctrl-single,pins = <
343 main_mmc1_pins_default: main-mmc1-default-pins {
344 bootph-all;
345 pinctrl-single,pins = <
357 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
358 pinctrl-single,pins = <
363 rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins {
364 pinctrl-single,pins = <
382 dp0_pins_default: dp0-default-pins {
383 pinctrl-single,pins = <
388 dp_pwr_en_pins_default: dp-pwr-en-default-pins {
389 pinctrl-single,pins = <
394 dss_vout0_pins_default: dss-vout0-default-pins {
395 pinctrl-single,pins = <
427 hdmi_hpd_pins_default: hdmi-hpd-default-pins {
428 pinctrl-single,pins = <
435 bootph-all;
436 pmic_irq_pins_default: pmic-irq-default-pins {
437 pinctrl-single,pins = <
443 wkup_uart0_pins_default: wkup-uart0-default-pins {
444 bootph-all;
445 pinctrl-single,pins = <
453 wkup_i2c0_pins_default: wkup-i2c0-default-pins {
454 bootph-all;
455 pinctrl-single,pins = <
461 mcu_uart0_pins_default: mcu-uart0-default-pins {
462 bootph-all;
463 pinctrl-single,pins = <
469 mcu_i2c0_pins_default: mcu-i2c0-default-pins {
470 pinctrl-single,pins = <
476 mcu_cpsw_pins_default: mcu-cpsw-default-pins {
477 pinctrl-single,pins = <
493 mcu_mdio_pins_default: mcu-mdio-default-pins {
494 pinctrl-single,pins = <
500 mcu_rpi_hdr1_gpio0_pins_default: mcu-rpi-hdr1-gpio0-default-pins {
501 pinctrl-single,pins = <
514 mcu_i2c1_pins_default: mcu-i2c1-default-pins {
515 pinctrl-single,pins = <
523 hdmi_pdn_pins_default: hdmi-pdn-default-pins {
524 pinctrl-single,pins = <
531 mcu_rpi_hdr2_gpio0_pins_default: mcu-rpi-hdr2-gpio0-default-pins {
532 pinctrl-single,pins = <
541 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
542 ti,mbox-rx = <0 0 0>;
543 ti,mbox-tx = <1 0 0>;
546 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
547 ti,mbox-rx = <2 0 0>;
548 ti,mbox-tx = <3 0 0>;
555 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
556 ti,mbox-rx = <0 0 0>;
557 ti,mbox-tx = <1 0 0>;
560 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
561 ti,mbox-rx = <2 0 0>;
562 ti,mbox-tx = <3 0 0>;
569 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
570 ti,mbox-rx = <0 0 0>;
571 ti,mbox-tx = <1 0 0>;
574 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
575 ti,mbox-rx = <2 0 0>;
576 ti,mbox-tx = <3 0 0>;
583 mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 {
584 ti,mbox-rx = <0 0 0>;
585 ti,mbox-tx = <1 0 0>;
588 mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 {
589 ti,mbox-rx = <2 0 0>;
590 ti,mbox-tx = <3 0 0>;
597 mbox_c71_0: mbox-c71-0 {
598 ti,mbox-rx = <0 0 0>;
599 ti,mbox-tx = <1 0 0>;
602 mbox_c71_1: mbox-c71-1 {
603 ti,mbox-rx = <2 0 0>;
604 ti,mbox-tx = <3 0 0>;
611 mbox_c71_2: mbox-c71-2 {
612 ti,mbox-rx = <0 0 0>;
613 ti,mbox-tx = <1 0 0>;
616 mbox_c71_3: mbox-c71-3 {
617 ti,mbox-rx = <2 0 0>;
618 ti,mbox-tx = <3 0 0>;
625 pinctrl-names = "default";
626 pinctrl-0 = <&wkup_uart0_pins_default>;
630 bootph-all;
632 pinctrl-names = "default";
633 pinctrl-0 = <&wkup_i2c0_pins_default>;
634 clock-frequency = <400000>;
637 /* AT24C512C-MAHM-T */
643 compatible = "ti,tps6594-q1";
645 system-power-controller;
646 pinctrl-names = "default";
647 pinctrl-0 = <&pmic_irq_pins_default>;
648 interrupt-parent = <&wkup_gpio0>;
650 gpio-controller;
651 #gpio-cells = <2>;
652 ti,primary-pmic;
653 buck12-supply = <&vsys_3v3>;
654 buck3-supply = <&vsys_3v3>;
655 buck4-supply = <&vsys_3v3>;
656 buck5-supply = <&vsys_3v3>;
657 ldo1-supply = <&vsys_3v3>;
658 ldo2-supply = <&vsys_3v3>;
659 ldo3-supply = <&vsys_3v3>;
660 ldo4-supply = <&vsys_3v3>;
664 regulator-name = "vdd_ddr_1v1";
665 regulator-min-microvolt = <1100000>;
666 regulator-max-microvolt = <1100000>;
667 regulator-boot-on;
668 regulator-always-on;
672 regulator-name = "vdd_ram_0v85";
673 regulator-min-microvolt = <850000>;
674 regulator-max-microvolt = <850000>;
675 regulator-boot-on;
676 regulator-always-on;
680 regulator-name = "vdd_io_1v8";
681 regulator-min-microvolt = <1800000>;
682 regulator-max-microvolt = <1800000>;
683 regulator-boot-on;
684 regulator-always-on;
688 regulator-name = "vdd_mcu_0v85";
689 regulator-min-microvolt = <850000>;
690 regulator-max-microvolt = <850000>;
691 regulator-boot-on;
692 regulator-always-on;
696 regulator-name = "vdd_mcuio_1v8";
697 regulator-min-microvolt = <1800000>;
698 regulator-max-microvolt = <1800000>;
699 regulator-boot-on;
700 regulator-always-on;
704 regulator-name = "vdd_mcuio_3v3";
705 regulator-min-microvolt = <3300000>;
706 regulator-max-microvolt = <3300000>;
707 regulator-boot-on;
708 regulator-always-on;
712 regulator-name = "vds_dll_0v8";
713 regulator-min-microvolt = <800000>;
714 regulator-max-microvolt = <800000>;
715 regulator-boot-on;
716 regulator-always-on;
720 regulator-name = "vda_mcu_1v8";
721 regulator-min-microvolt = <1800000>;
722 regulator-max-microvolt = <1800000>;
723 regulator-boot-on;
724 regulator-always-on;
732 pinctrl-names = "default";
733 pinctrl-0 = <&mcu_rpi_hdr1_gpio0_pins_default>, <&mcu_rpi_hdr2_gpio0_pins_default>;
737 bootph-all;
739 pinctrl-names = "default";
740 pinctrl-0 = <&mcu_uart0_pins_default>;
745 pinctrl-names = "default";
746 pinctrl-0 = <&mcu_i2c0_pins_default>;
747 clock-frequency = <400000>;
751 bootph-all;
753 pinctrl-names = "default";
754 pinctrl-0 = <&main_uart8_pins_default>;
759 pinctrl-names = "default";
760 pinctrl-0 = <&main_i2c0_pins_default>;
761 clock-frequency = <400000>;
766 gpio-controller;
767 #gpio-cells = <2>;
768 gpio-line-names = "BOARDID_EEPROM_WP", "CAN_STB", "GPIO_uSD_PWR_EN",
778 bootph-all;
781 non-removable;
782 ti,driver-strength-ohm = <50>;
783 disable-wp;
787 bootph-all;
790 pinctrl-0 = <&main_mmc1_pins_default>;
791 pinctrl-names = "default";
792 disable-wp;
793 vmmc-supply = <&vdd_mmc1>;
794 vqmmc-supply = <&vdd_sd_dv>;
799 pinctrl-names = "default";
800 pinctrl-0 = <&rpi_header_gpio0_pins_default>;
805 pinctrl-names = "default";
806 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
810 mcu_phy0: ethernet-phy@0 {
812 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
813 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
814 ti,min-output-impedance;
820 phy-mode = "rgmii-rxid";
821 phy-handle = <&mcu_phy0>;
826 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
832 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
838 memory-region = <&main_r5fss0_core0_dma_memory_region>,
844 memory-region = <&main_r5fss0_core1_dma_memory_region>,
850 memory-region = <&main_r5fss1_core0_dma_memory_region>,
856 memory-region = <&main_r5fss1_core1_dma_memory_region>,
862 memory-region = <&main_r5fss2_core0_dma_memory_region>,
868 memory-region = <&main_r5fss2_core1_dma_memory_region>,
875 memory-region = <&c71_0_dma_memory_region>,
882 memory-region = <&c71_1_dma_memory_region>,
889 memory-region = <&c71_2_dma_memory_region>,
896 memory-region = <&c71_3_dma_memory_region>,
906 pinctrl-names = "default";
907 pinctrl-0 = <&mcu_i2c1_pins_default>;
908 clock-frequency = <100000>;
913 clock-frequency = <100000000>;
918 pinctrl-names = "default";
919 pinctrl-0 = <&dss_vout0_pins_default>;
920 assigned-clocks = <&k3_clks 218 2>,
924 assigned-clock-parents = <&k3_clks 218 3>,
938 cdns,num-lanes = <4>;
939 #phy-cells = <0>;
940 cdns,phy-type = <PHY_TYPE_DP>;
948 pinctrl-names = "default";
949 pinctrl-0 = <&dp0_pins_default>;
951 phy-names = "dpphy";
955 #address-cells = <1>;
956 #size-cells = <0>;
963 remote-endpoint = <&dp0_in>;
972 remote-endpoint = <&tfp410_in>;
983 remote-endpoint = <&dpi0_out>;
991 remote-endpoint = <&dp0_connector_in>;