Lines Matching +full:davinci +full:- +full:gpio +full:- +full:unbanked
1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
9 compatible = "mmio-sram";
11 #address-cells = <1>;
12 #size-cells = <1>;
16 gic500: interrupt-controller@1800000 {
17 compatible = "arm,gic-v3";
18 #address-cells = <2>;
19 #size-cells = <2>;
21 #interrupt-cells = <3>;
22 interrupt-controller;
34 gic_its: msi-controller@1820000 {
35 compatible = "arm,gic-v3-its";
37 socionext,synquacer-pre-its = <0x1000000 0x400000>;
38 msi-controller;
39 #msi-cells = <1>;
44 compatible = "simple-bus";
46 #address-cells = <1>;
47 #size-cells = <1>;
51 compatible = "ti,am654-phy-gmii-sel";
53 #phy-cells = <1>;
56 epwm_tbclk: clock-controller@4130 {
57 compatible = "ti,am62-epwm-tbclk";
59 #clock-cells = <1>;
64 compatible = "simple-bus";
65 #address-cells = <2>;
66 #size-cells = <2>;
67 dma-ranges;
69 bootph-all;
71 ti,sci-dev-id = <25>;
74 compatible = "ti,am654-secure-proxy";
75 #mbox-cells = <1>;
76 reg-names = "target_data", "rt", "scfg";
80 interrupt-names = "rx_012";
82 bootph-all;
85 inta_main_dmss: interrupt-controller@48000000 {
86 compatible = "ti,sci-inta";
88 #interrupt-cells = <0>;
89 interrupt-controller;
90 interrupt-parent = <&gic500>;
91 msi-controller;
93 ti,sci-dev-id = <28>;
94 ti,interrupt-ranges = <5 69 35>;
95 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>;
98 main_bcdma: dma-controller@485c0100 {
99 compatible = "ti,am64-dmss-bcdma";
109 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt",
111 msi-parent = <&inta_main_dmss>;
112 #dma-cells = <3>;
115 ti,sci-dev-id = <26>;
116 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */
117 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */
118 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */
119 bootph-all;
122 main_pktdma: dma-controller@485c0000 {
123 compatible = "ti,am64-dmss-pktdma";
132 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt",
134 msi-parent = <&inta_main_dmss>;
135 #dma-cells = <2>;
136 bootph-all;
139 ti,sci-dev-id = <30>;
140 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */
144 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */
148 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */
154 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */
161 dmsc: system-controller@44043000 {
162 compatible = "ti,k2g-sci";
163 ti,host-id = <12>;
164 mbox-names = "rx", "tx";
167 reg-names = "debug_messages";
169 bootph-all;
171 k3_pds: power-controller {
172 compatible = "ti,sci-pm-domain";
173 #power-domain-cells = <2>;
174 bootph-all;
177 k3_clks: clock-controller {
178 compatible = "ti,k2g-sci-clk";
179 #clock-cells = <2>;
180 bootph-all;
183 k3_reset: reset-controller {
184 compatible = "ti,sci-reset";
185 #reset-cells = <2>;
186 bootph-all;
191 compatible = "ti,am62-sa3ul";
193 #address-cells = <2>;
194 #size-cells = <2>;
199 dma-names = "tx", "rx1", "rx2";
203 compatible = "ti,am654-secure-proxy";
204 #mbox-cells = <1>;
205 reg-names = "target_data", "rt", "scfg";
212 * firmware on non-MPU processors
215 bootph-all;
219 compatible = "pinctrl-single";
221 #pinctrl-cells = <1>;
222 pinctrl-single,register-width = <32>;
223 pinctrl-single,function-mask = <0xffffffff>;
224 bootph-all;
228 compatible = "ti,j721e-esm";
230 ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
231 bootph-pre-ram;
235 compatible = "ti,am654-timer";
239 clock-names = "fck";
240 assigned-clocks = <&k3_clks 36 2>;
241 assigned-clock-parents = <&k3_clks 36 3>;
242 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>;
243 ti,timer-pwm;
244 bootph-all;
248 compatible = "ti,am654-timer";
252 clock-names = "fck";
253 assigned-clocks = <&k3_clks 37 2>;
254 assigned-clock-parents = <&k3_clks 37 3>;
255 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>;
256 ti,timer-pwm;
260 compatible = "ti,am654-timer";
264 clock-names = "fck";
265 assigned-clocks = <&k3_clks 38 2>;
266 assigned-clock-parents = <&k3_clks 38 3>;
267 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
268 ti,timer-pwm;
272 compatible = "ti,am654-timer";
276 clock-names = "fck";
277 assigned-clocks = <&k3_clks 39 2>;
278 assigned-clock-parents = <&k3_clks 39 3>;
279 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
280 ti,timer-pwm;
284 compatible = "ti,am654-timer";
288 clock-names = "fck";
289 assigned-clocks = <&k3_clks 40 2>;
290 assigned-clock-parents = <&k3_clks 40 3>;
291 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
292 ti,timer-pwm;
296 compatible = "ti,am654-timer";
300 clock-names = "fck";
301 assigned-clocks = <&k3_clks 41 2>;
302 assigned-clock-parents = <&k3_clks 41 3>;
303 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
304 ti,timer-pwm;
308 compatible = "ti,am654-timer";
312 clock-names = "fck";
313 assigned-clocks = <&k3_clks 42 2>;
314 assigned-clock-parents = <&k3_clks 42 3>;
315 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
316 ti,timer-pwm;
320 compatible = "ti,am654-timer";
324 clock-names = "fck";
325 assigned-clocks = <&k3_clks 43 2>;
326 assigned-clock-parents = <&k3_clks 43 3>;
327 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
328 ti,timer-pwm;
332 compatible = "ti,am64-uart", "ti,am654-uart";
335 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
337 clock-names = "fclk";
342 compatible = "ti,am64-uart", "ti,am654-uart";
345 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
347 clock-names = "fclk";
352 compatible = "ti,am64-uart", "ti,am654-uart";
355 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
357 clock-names = "fclk";
362 compatible = "ti,am64-uart", "ti,am654-uart";
365 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
367 clock-names = "fclk";
372 compatible = "ti,am64-uart", "ti,am654-uart";
375 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>;
377 clock-names = "fclk";
382 compatible = "ti,am64-uart", "ti,am654-uart";
385 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;
387 clock-names = "fclk";
392 compatible = "ti,am64-uart", "ti,am654-uart";
395 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;
397 clock-names = "fclk";
402 compatible = "ti,am64-i2c", "ti,omap4-i2c";
405 #address-cells = <1>;
406 #size-cells = <0>;
407 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
409 clock-names = "fck";
414 compatible = "ti,am64-i2c", "ti,omap4-i2c";
417 #address-cells = <1>;
418 #size-cells = <0>;
419 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
421 clock-names = "fck";
426 compatible = "ti,am64-i2c", "ti,omap4-i2c";
429 #address-cells = <1>;
430 #size-cells = <0>;
431 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
433 clock-names = "fck";
438 compatible = "ti,am64-i2c", "ti,omap4-i2c";
441 #address-cells = <1>;
442 #size-cells = <0>;
443 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
445 clock-names = "fck";
450 compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
453 #address-cells = <1>;
454 #size-cells = <0>;
455 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
461 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
464 #address-cells = <1>;
465 #size-cells = <0>;
466 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
472 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
475 #address-cells = <1>;
476 #size-cells = <0>;
477 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
482 main_gpio_intr: interrupt-controller@a00000 {
483 compatible = "ti,sci-intr";
485 ti,intr-trigger-type = <1>;
486 interrupt-controller;
487 interrupt-parent = <&gic500>;
488 #interrupt-cells = <1>;
490 ti,sci-dev-id = <3>;
491 ti,interrupt-ranges = <0 32 16>;
494 main_gpio0: gpio@600000 {
495 compatible = "ti,am64-gpio", "ti,keystone-gpio";
497 gpio-controller;
498 #gpio-cells = <2>;
499 interrupt-parent = <&main_gpio_intr>;
502 interrupt-controller;
503 #interrupt-cells = <2>;
505 ti,davinci-gpio-unbanked = <0>;
506 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
508 clock-names = "gpio";
511 main_gpio1: gpio@601000 {
512 compatible = "ti,am64-gpio", "ti,keystone-gpio";
514 gpio-controller;
515 #gpio-cells = <2>;
516 interrupt-parent = <&main_gpio_intr>;
519 interrupt-controller;
520 #interrupt-cells = <2>;
522 ti,davinci-gpio-unbanked = <0>;
523 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
525 clock-names = "gpio";
529 compatible = "ti,am64-sdhci-8bit";
532 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>;
534 clock-names = "clk_ahb", "clk_xin";
535 assigned-clocks = <&k3_clks 57 2>;
536 assigned-clock-parents = <&k3_clks 57 4>;
537 ti,otap-del-sel-legacy = <0x0>;
542 compatible = "ti,am62-sdhci";
545 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>;
547 clock-names = "clk_ahb", "clk_xin";
548 ti,otap-del-sel-legacy = <0x8>;
553 compatible = "ti,am62-sdhci";
556 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
558 clock-names = "clk_ahb", "clk_xin";
559 ti,otap-del-sel-legacy = <0x8>;
564 compatible = "simple-bus";
566 #address-cells = <2>;
567 #size-cells = <2>;
571 compatible = "ti,am654-ospi", "cdns,qspi-nor";
575 cdns,fifo-depth = <256>;
576 cdns,fifo-width = <4>;
577 cdns,trigger-address = <0x0>;
579 assigned-clocks = <&k3_clks 75 7>;
580 assigned-clock-parents = <&k3_clks 75 8>;
581 assigned-clock-rates = <166666666>;
582 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>;
583 #address-cells = <1>;
584 #size-cells = <0>;
590 compatible = "ti,am642-cpsw-nuss";
591 #address-cells = <2>;
592 #size-cells = <2>;
594 reg-names = "cpsw_nuss";
597 assigned-clocks = <&k3_clks 13 3>;
598 assigned-clock-parents = <&k3_clks 13 11>;
599 clock-names = "fck";
600 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>;
611 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6",
614 ethernet-ports {
615 #address-cells = <1>;
616 #size-cells = <0>;
620 ti,mac-only;
623 mac-address = [00 00 00 00 00 00];
628 ti,mac-only;
631 mac-address = [00 00 00 00 00 00];
636 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
638 #address-cells = <1>;
639 #size-cells = <0>;
641 clock-names = "fck";
647 compatible = "ti,j721e-cpts";
650 clock-names = "cpts";
651 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
652 interrupt-names = "cpts";
653 ti,cpts-ext-ts-inputs = <4>;
654 ti,cpts-periodic-outputs = <2>;
659 compatible = "ti,am64-hwspinlock";
661 #hwlock-cells = <1>;
665 compatible = "ti,am64-mailbox";
668 #mbox-cells = <1>;
669 ti,mbox-num-users = <4>;
670 ti,mbox-num-fifos = <16>;
674 compatible = "ti,am64-mailbox";
677 #mbox-cells = <1>;
678 ti,mbox-num-users = <4>;
679 ti,mbox-num-fifos = <16>;
683 compatible = "ti,am64-mailbox";
686 #mbox-cells = <1>;
687 ti,mbox-num-users = <4>;
688 ti,mbox-num-fifos = <16>;
692 compatible = "ti,am64-mailbox";
695 #mbox-cells = <1>;
696 ti,mbox-num-users = <4>;
697 ti,mbox-num-fifos = <16>;
701 compatible = "ti,am3352-ecap";
702 #pwm-cells = <3>;
704 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>;
706 clock-names = "fck";
711 compatible = "ti,am3352-ecap";
712 #pwm-cells = <3>;
714 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>;
716 clock-names = "fck";
721 compatible = "ti,am3352-ecap";
722 #pwm-cells = <3>;
724 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>;
726 clock-names = "fck";
734 reg-names = "m_can", "message_ram";
735 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
737 clock-names = "hclk", "cclk";
740 interrupt-names = "int0", "int1";
741 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
749 reg-names = "m_can", "message_ram";
750 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
752 clock-names = "hclk", "cclk";
755 interrupt-names = "int0", "int1";
756 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
761 compatible = "ti,j7-rti-wdt";
764 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>;
765 assigned-clocks = <&k3_clks 125 0>;
766 assigned-clock-parents = <&k3_clks 125 2>;
770 compatible = "ti,j7-rti-wdt";
773 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>;
774 assigned-clocks = <&k3_clks 126 0>;
775 assigned-clock-parents = <&k3_clks 126 2>;
779 compatible = "ti,j7-rti-wdt";
782 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>;
783 assigned-clocks = <&k3_clks 127 0>;
784 assigned-clock-parents = <&k3_clks 127 2>;
788 compatible = "ti,j7-rti-wdt";
791 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>;
792 assigned-clocks = <&k3_clks 128 0>;
793 assigned-clock-parents = <&k3_clks 128 2>;
797 compatible = "ti,j7-rti-wdt";
800 power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>;
801 assigned-clocks = <&k3_clks 130 0>;
802 assigned-clock-parents = <&k3_clks 130 2>;
806 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
807 #pwm-cells = <3>;
809 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>;
811 clock-names = "tbclk", "fck";
816 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
817 #pwm-cells = <3>;
819 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>;
821 clock-names = "tbclk", "fck";
826 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm";
827 #pwm-cells = <3>;
829 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>;
831 clock-names = "tbclk", "fck";
835 mcasp0: audio-controller@2b00000 {
836 compatible = "ti,am33xx-mcasp-audio";
839 reg-names = "mpu", "dat";
842 interrupt-names = "tx", "rx";
845 dma-names = "tx", "rx";
848 clock-names = "fck";
849 assigned-clocks = <&k3_clks 190 0>;
850 assigned-clock-parents = <&k3_clks 190 2>;
851 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
855 mcasp1: audio-controller@2b10000 {
856 compatible = "ti,am33xx-mcasp-audio";
859 reg-names = "mpu", "dat";
862 interrupt-names = "tx", "rx";
865 dma-names = "tx", "rx";
868 clock-names = "fck";
869 assigned-clocks = <&k3_clks 191 0>;
870 assigned-clock-parents = <&k3_clks 191 2>;
871 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
875 mcasp2: audio-controller@2b20000 {
876 compatible = "ti,am33xx-mcasp-audio";
879 reg-names = "mpu", "dat";
882 interrupt-names = "tx", "rx";
885 dma-names = "tx", "rx";
888 clock-names = "fck";
889 assigned-clocks = <&k3_clks 192 0>;
890 assigned-clock-parents = <&k3_clks 192 2>;
891 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;