Lines Matching +full:0 +full:x400
14 #size-cells = <0>;
16 cpu0: cpu@0 {
19 reg = <0>;
33 arm,smc-id = <0xb200005a>;
39 #clock-cells = <0>;
45 #clock-cells = <0>;
51 #clock-cells = <0>;
66 #size-cells = <0>;
67 linaro,optee-channel-id = <0>;
70 reg = <0x14>;
75 reg = <0x16>;
86 reg = <0x0 0x4ac10000 0x0 0x1000>,
87 <0x0 0x4ac20000 0x0 0x2000>,
88 <0x0 0x4ac40000 0x0 0x2000>,
89 <0x0 0x4ac60000 0x0 0x2000>;
107 soc@0 {
112 ranges = <0x0 0x0 0x0 0x80000000>;
116 reg = <0x42080000 0x1000>;
123 reg = <0x400e0000 0x400>;
131 arm,primecell-periphid = <0x00353180>;
132 reg = <0x48220000 0x400>, <0x44230400 0x8>;
145 reg = <0x44000000 0x1000>;
150 reg = <0x24 0x4>;
154 reg = <0x1e8 0x1>;
155 bits = <0 3>;
161 reg = <0x44230000 0x10000>;
168 ranges = <0 0x44240000 0xa0400>;
176 reg = <0x0 0x400>;
187 reg = <0x10000 0x400>;
198 reg = <0x20000 0x400>;
209 reg = <0x30000 0x400>;
220 reg = <0x40000 0x400>;
231 reg = <0x50000 0x400>;
242 reg = <0x60000 0x400>;
253 reg = <0x70000 0x400>;
264 reg = <0x80000 0x400>;
275 reg = <0x90000 0x400>;
286 reg = <0xa0000 0x400>;
297 ranges = <0 0x46200000 0x400>;
305 reg = <0 0x400>;