dts/sprd/ums9620.dtsi

1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 	interrupt-parent = <&gic>;
12 	#address-cells = <2>;
13 	#size-cells = <2>;
16 		#address-cells = <2>;
17 		#size-cells = <0>;
19 		cpu-map {
48 		CPU0: cpu@0 {
50 			compatible = "arm,cortex-a55";
51 			reg = <0x0 0x0>;
52 			enable-method = "psci";
53 			cpu-idle-states = <&LIT_CORE_PD>;
58 			compatible = "arm,cortex-a55";
59 			reg = <0x0 0x100>;
60 			enable-method = "psci";
61 			cpu-idle-states = <&LIT_CORE_PD>;
66 			compatible = "arm,cortex-a55";
67 			reg = <0x0 0x200>;
68 			enable-method = "psci";
69 			cpu-idle-states = <&LIT_CORE_PD>;
74 			compatible = "arm,cortex-a55";
75 			reg = <0x0 0x300>;
76 			enable-method = "psci";
77 			cpu-idle-states = <&LIT_CORE_PD>;
82 			compatible = "arm,cortex-a76";
83 			reg = <0x0 0x400>;
84 			enable-method = "psci";
85 			cpu-idle-states = <&BIG_CORE_PD>;
90 			compatible = "arm,cortex-a76";
91 			reg = <0x0 0x500>;
92 			enable-method = "psci";
93 			cpu-idle-states = <&BIG_CORE_PD>;
98 			compatible = "arm,cortex-a76";
99 			reg = <0x0 0x600>;
100 			enable-method = "psci";
101 			cpu-idle-states = <&BIG_CORE_PD>;
106 			compatible = "arm,cortex-a76";
107 			reg = <0x0 0x700>;
108 			enable-method = "psci";
109 			cpu-idle-states = <&BIG_CORE_PD>;
113 	idle-states {
114 		entry-method = "psci";
115 		LIT_CORE_PD: cpu-pd-lit {
116 			compatible = "arm,idle-state";
117 			entry-latency-us = <1000>;
118 			exit-latency-us = <500>;
119 			min-residency-us = <2500>;
120 			local-timer-stop;
121 			arm,psci-suspend-param = <0x00010000>;
124 		BIG_CORE_PD: cpu-pd-big {
125 			compatible = "arm,idle-state";
126 			entry-latency-us = <4000>;
127 			exit-latency-us = <4000>;
128 			min-residency-us = <10000>;
129 			local-timer-stop;
130 			arm,psci-suspend-param = <0x00010000>;
134 	psci {
135 		compatible = "arm,psci-0.2";
140 		compatible = "arm,armv8-timer";
142 			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */
148 		compatible = "arm,armv8-pmuv3";
160 		compatible = "simple-bus";
162 		#address-cells = <2>;
163 		#size-cells = <2>;
165 		gic: interrupt-controller@12000000 {
166 			compatible = "arm,gic-v3";
167 			reg = <0x0 0x12000000 0 0x20000>,	/* GICD */
168 			      <0x0 0x12040000 0 0x100000>;	/* GICR */
169 			#interrupt-cells = <3>;
170 			#address-cells = <2>;
171 			#size-cells = <2>;
172 			redistributor-stride = <0x0 0x20000>;	/* 128KB stride */
173 			#redistributor-regions = <1>;
174 			interrupt-controller;
179 			compatible = "simple-bus";
180 			ranges = <0 0 0x20200000 0x100000>;
181 			#address-cells = <1>;
182 			#size-cells = <1>;
184 			uart0: serial@0 {
185 				compatible = "sprd,ums9620-uart",
186 					     "sprd,sc9836-uart";
187 				reg = <0 0x100>;
194 				compatible = "sprd,ums9620-uart",
195 					     "sprd,sc9836-uart";
196 				reg = <0x10000 0x100>;
204 	ext_26m: clk-26m {
205 		compatible = "fixed-clock";
206 		#clock-cells = <0>;
207 		clock-frequency = <26000000>;
208 		clock-output-names = "ext-26m";
211 	ext_4m: clk-4m {
212 		compatible = "fixed-clock";
213 		#clock-cells = <0>;
214 		clock-frequency = <4000000>;
215 		clock-output-names = "ext-4m";
218 	ext_32k: clk-32k {
219 		compatible = "fixed-clock";
220 		#clock-cells = <0>;
221 		clock-frequency = <32768>;
222 		clock-output-names = "ext-32k";
225 	rco_100m: clk-100m {
226 		compatible = "fixed-clock";
227 		#clock-cells = <0>;
228 		clock-frequency = <100000000>;
229 		clock-output-names = "rco-100m";
232 	dphy_312m5: dphy-312m5 {
233 		compatible = "fixed-clock";
234 		#clock-cells = <0>;
235 		clock-frequency = <312500000>;
236 		clock-output-names = "dphy-312m5";
239 	dphy_416m7: dphy-416m7 {
240 		compatible = "fixed-clock";
241 		#clock-cells = <0>;
242 		clock-frequency = <416700000>;
243 		clock-output-names = "dphy-416m7";